TSMC qualifies Applied Materials’ gate stack system

May 10, 2005 – Applied Materials has announced that Taiwan Semiconductor Manufacturing Co. (TSMC) has qualified the Applied Centura Gate Stack system with decoupled plasma nitridation (DPN) technology for all its 65nm-generation transistor fabrication processes.

The companies said the advanced technology enabled TSMC to achieve its 65nm equivalent oxide thickness (EOT) scaling targets while increasing device speed.

“Applied’s single-wafer gate stack system has played a significant role in TSMC’s leadership in advanced transistor fabrication,” said Mong-Song Liang, senior director, TSMC’s Advanced Modules Technology Division, R&D.

The Applied Gate Stack system provides film interface control by integrating DPN, Radiance RTP, in situ steam generation (ISSG) oxidation and polysilicon deposition processes on the Centura platform. TSMC already uses the 300mm Applied Centura gate stack system in its fabs, where its advanced single-wafer technology and multi-process integration capabilities have made it tool of record for transistor manufacturing.

“TSMC is a world leader in high-performance transistor fabrication, and we are delighted to contribute to their extension of oxynitride gate dielectric technology to 65nm,” said Dr. Randhir Thakur, group VP and GM of Applied Materials’ Front End Products group.


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