By J. Robert Lineback, Senior Technical Editor
Nearly four years into its campaign to change the way ICs are routed for interconnects, the X Initiative group believes 2005 will be the first year when multiple products are launched based on the X Architecture. The new layout wires chip functions together diagonally instead of traditional layouts using right-angle connections, aiming to boost performance and make chips smaller.
“We are seeing more interest and starting serious engagements with many customers worldwide,” said Patrick Lin, chief system-on-chip (SoC) architect at United Microelectronics Corp. Taiwan-based UMC, the world’s second largest silicon foundry, announced on April 11 that it has qualified 90nm process design rules for X Architecture-based chips. UMC already is producing prototypes of X Architecture-based ICs for some fabless companies and integrated device manufacturers (IDMs), Lin told WaferNews.
The X Initiative group’s roster of 40 companies, including fab equipment suppliers, maskmakers, design automation houses, and foundries, believes diagonally routed ICs will shorten interconnect wiring by up to 20% across a die and reduce the number of vias by up to 30%. Last June, Japan’s Toshiba Corp. became the first company to announce the launch of a commercial SoC product that used X Architecture layouts (see WaferNews, V11n24, June 14, 2004). The 130nm IC, which integrates functions for digital TVs and multimedia systems, has been slated to enter mass production in 2Q05 for a European customer.
UMC’s Lin and X Initiative marketing director Ketan Joshi were unable to say how many products are now being developed with diagonal interconnects vs. conventional “Manhattan” layouts that resemble street grids plotted on x–y coordinates. “Some [fabless companies] feel X gives them a competitive advantage, and they do not want to disclose this too early,” stated Joshi, who works at Cadence Design Systems Inc. in San Jose, CA.
Among the serious product engagements in X Architecture layouts, UMC is seeing strong interest in wireless baseband and broadband networking applications, Lin said. Many early product designs based on X Architecture layouts will combine diagonal wiring — for upper “global” interconnect layers — with Manhattan layout grids for internal routing inside memory or logic functional blocks, he said. — J.R.L.