Moore’s Law has taken us from microelectronics to nanoelectronics. The need to stay on the materials treadmill has never been greater. Add the fact that the world’s customer-base for digital technologies is expanding across the globe. Concerns surrounding thermal management and robustness for physically smaller systems will only increase. Compatibility between materials systems used in silicon fabrication, first-level packaging, and electronic systems is becoming challenging.
Materials challenges exist in developing new materials and using existing materials in new applications. We are moving into the regime of heterogeneous integration of various silicon types into one component, where using existing materials in new combinations will invoke design and processing considerations that push the envelope of materials compatibility. This will require more integrated development across design, process, and materials disciplines. Interconnect solutions of the recent past are examples of the type of work ahead of us. Silicon performance increases and power optimization have required concerted efforts to decrease resistive-capacitive (RC) parasitics. Interconnects on the silicon device have changed from Al to Cu, and driven changes in the metallurgy of packaging first-level interconnects. Bond pad metallization stacks have been re-optimized for intermetallic compound formation between the silicon metallization and the wire bond material. Packages with flip chip (solder bump) interconnects that provide low impedance are an increasing percentage of the total volume of components, driving extensive work to optimize metallurgies at the Si-to-bump and bump-to-package land pattern interface for strength and creep resistance.
To decrease C, the inner-layer dielectric (ILD) materials’ dielectric constant, k, has been lowered, mainly by adding porosity. The more porous low-k ILD is inherently more fragile since elastic modulus and hardness decrease rapidly with porosity. They are susceptible to the mechanical stress in the “Si” stack from CTE mismatch and mechanically induced strain. A recent device performance enhancement was obtained by straining the silicon lattice in the MOS transistor channel to increase carrier mobility. The packaging of devices containing strained silicon must maintain the deliberately introduced strain states in the silicon by accounting for the residual stresses from assembly.
The use of underfill materials between the silicon and the package substrate is one approach to distributing stress in flip chip packages. As inter-bump pitch and gap height are reduced to obtain increasing I/O density, modifications in the filler and material rheology have been needed to ensure adequate coverage within existing manufacturing throughput times. Balancing these modifications is the requirement for finer control on fillet length and height, as flip chip interconnects move into the realm of chip-scale packaging. The engineering design of surface tension and wetting characteristics of underfill materials has come into an increased role in the formulation of this class of materials. Lead-free bump materials with different surface characteristics and more rigid bumps are being implemented, at the same time lower-k dielectrics are becoming increasingly fragile.
Large advances in power control at the silicon level are being made. The shrinking of packages for mobility and stacking of memory makes heat dissipation more difficult at the individual package level, as does the tight packing of multiple devices into one mobile application.
Similar concerns about low viscosity, improved adhesion, moisture resistance, compliancy, toughness, and CTE are being addressed for molding compounds and die-attach adhesives and films used for stacked-die packages. In addition, indirect materials used in processing such as temporary adhesives, fluxes, coatings, and photoresists used during assembly processes are increasing in complexity. Tailoring the chemistries of such materials has become crucial to eliminate detrimental interactions of these materials with in situ direct materials or residues left after processing
With further demand for materials properties above and beyond today’s capabilities, the need for design and integration of materials solutions with specific electrical, mechanical, thermal, manufacturability, and environmental performance becomes more important. How these areas of engineering design will address future performance demands must be the focus of our industry over the next few years. Potentially useful physical chemical and materials solutions will only be exploited successfully through innovation and skillful integration.
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NASSER GRAYELI, director of Assembly Technology Development, VP of the Technology Manufacturing Group, may be contacted at Intel Corp., P.O. Box 58119, Santa Clara, CA 95052-8119.