Renesas’ gate design was created using Synopsys’ physical design solution &#8212 the Design Compiler product for synthesis, Power Compiler for dynamic and leakage power optimization, Physical Compiler and Astro products for physical implementation, and Star-RCXT for full-chip parasitic extraction. The yield-aware routing optimization techniques in the Astro product, such as redundant via insertion, helped Renesas minimize impact on timing-critical nets and optimize for yield, while maintaining a predictable convergence to timing closure.