BY HANK HOGAN
AUSTIN, Texas-The need for and difficulty of removing surface particles without damaging circuit features, and the increasing trend of mask cleaning borrowing from wafer-cleaning technologies, were key themes that emerged from the seventh annual conference on surface preparation cleaning, “Emerging Technologies in Semiconductor Surface Preparation,” sponsored by SEMATECH (www.sematech.org).
The April conference focused on trends in surface preparation and the cleaning of semiconductors and photolithographic masks.
Presenters noted that particle removal has become especially challenging for the 45-nanometer (nm) and below process nodes, compared to cleaning today’s state-of-the-art 65-nm node. Features are finer in these more advanced processes, making damage-free particle removal more critical. And these particles can come from just about anywhere, notes Naim Moumen, SEMATECH’s project manager for advanced gate cleans. “It could be from both processes and cross- contamination; it could be from cleanrooms,” he says.
One proposed solution is single-wafer cleaning, where cleaning can be fine-tuned and made more uniform than what is currently possible with a batch cleaning approach. Such uniformity will result in a more precise and careful cleaning, claims Harald Okorn-Schmidt, vice president of global research for SEZ AG (Villach, Austria), which manufactures single-wafer cleaning systems.
In addition to the increased potential for less wafer damage, Okorn-Schmidt foresees another dividend from using compact, single-wafer methods: “Valuable cleanroom space can be saved.”
Companies like Applied Materials, Inc. (Santa Clara, Calif.; www.appliedmaterials.com), meanwhile, offer a mixed-fluid jet approach to wafer cleaning. Steven Verhaverbeke, chief technology officer of Applied’s wet-clean division, notes that this approach typically uses nitrogen gas and water, with the maximum force well controlled. In recent tests, Verhaverbeke told conference attendees, particle removal efficiency using the mixed-fluid jet approach topped 90 percent without etching the surface and without damaging 65-nm polysilicon lines.
As for trends in mask cleaning, conference presenters observed that mask cleaning is increasingly borrowing from wafer-cleaning technology because it has outpaced established mask-cleaning methods. “The older methods have worked quite well up until the past few years,” says Louis Kindt, a mask process engineer with IBM Microelectronics (Essex Junction, Vt.; www.ibm.com/chips), but that situation has changed as mask features have become smaller.
In addition, Kindt says, the increase in wafer size to 300 millimeters has made masks and wafers of roughly comparable dimensions. So, equipment suppliers can use similar tools for cleaning both, although the fixturing must be different.
According to Moumen and fellow conference organizer Joel Barnett, a senior member of SEMATECH’s technical staff, 200 industry participants from 70 organizations-ranging from manufacturers and suppliers to universities-attended the April meeting. III