(June 14, 2005) Kyoto, Japan — Texas Instruments (TI), together with its research and evelopment partners and peers, is presenting papers escribing key accomplishments on advanced materials and manufacturing process development at the 2005 Symposium on VLSI Technology. TI’s contribution highlights a comprehensive R&D strategy that combines in-house initiatives with close collaboration among industry consortia and universities to deliver semiconductor breakthroughs to TI’s customers.
“TI is among the leaders in overcoming the challenges of semiconductor scaling, and plans to maintain this position in the advancement of future transistor technology,” says Dr. Hans Stork, TI’s CTO. “The research presented at the VLSI Symposium will continue TI’s development of high-performance, low-cost semiconductor products with highly integrated system-on-a-chip (SoC) implementations.”
At the VLSI Symposium, TI and its partners will present a first-time demonstration of the scalability of fully silicided, nickel silicide (NiSi) gates to 30-nm and below, easing the transition from current polysilicon gate electrodes to full-silicidation-of-polysilicon (FuSi), and resulting in cost-effective integration of metal gates. TI also participates in research efforts that focus on advancing non-planar triple-gate devices, and will discuss fabrication of the industry’s smallest 6T-SRAM cell with multi-gate devices, which is based upon work done within the IMEC European nanoelectronics research center as part of a sub-45-nm CMOS program. TI uses 6T SRAM cells as the primary embedded memory in its CMOS products. Migrating to triple-gate non-planar transistors may extend the use of 6T SRAM cells to the 32-nm node or beyond, maintaining design compatibility with conventional SRAM approaches and significantly shrinking previously designed triple-gate SRAM device cells, further improving performance and integration options.
TI is also presenting research through work with SEMATECH on the compatibility of non-planar multi-gate transistor approaches with conventional CMOS approaches by introducing strain to improve the drive current of future transistors by as much as 25%. These advancements result from TI’s overall external research strategy to evaluate the feasibility of materials, processes, and device concepts in the pre-competitive stage. TI’s in-house R&D technology development teams then shift attention to development in its manufacturing facilities in close collaboration with customers to meet their key priorities. TI’s overall R&D addresses many topics, and focuses on closing key gaps in:
(June 15, 2005) New York, N.Y. — There exists great concern about the environmental, health, and safety (EHS) risks of nanoparticles — tiny, engineered particles of matter might harm workers, consumers, or the environment. Such EHS risks can be appropriately addressed using well-established risk management techniques, according to a new report from Lux Research, titled “A Prudent Approach to Nanotech Environmental, Health, and Safety Risks.”
“If definitive data was available about the toxicity and environmental impact of nanoparticles, there would be no debate,” claims Matthew M. Nordan, Lux Research’s VP of research. “However, today, fundamental research in the field is just getting underway. Lab-based studies are thin on the ground, and those that have been published sometimes conflict. We recommend that corporations and start-ups assess nanotech EHS issues based on existing risk management frameworks — substituting informed, conservative proxies for definitive data — to make wise commercialization decisions.”
To assess nanotech EHS risks, Lux Research conducted exhaustive secondary research on the issue and interviewed 42 relevant start-up executives, academics, government agency representatives, non-governmental organization representatives, insurance company executives, and corporate EHS officers. The report’s findings include: