BY MARCOS KARNEZOS
Feature-rich cell phones, pocket PCs, digital cameras, and other handheld consumer products require maximum functional integration, including memory, DSP, ASIC, RF, MEMs, and other devices in the smallest footprint, lowest profile, and lowest cost package available. These requirements have driven most recent developments in packaging, all grouped under the generic name of system-in-package (SiP) to emphasize the package-level system integration. The old multichip module (MCM) that assembles chips and passives side-by-side on the substrate in one package does not provide either the footprint or the cost reductions experienced by these products. 3-D packages stack tested-good-die and pre-tested packages and other passive components in one standard package that is hard to distinguish from a conventional one-chip package. 3-D packaging types are often characterized by how they are stacked as chips, packages, and passives.
Stacked-die-packages (SDP) consist of bare die stacked and interconnected, using wire bond and flip chip connections in one standard package. It offers the smallest footprint with the thinnest profile and lowest packaging cost, but the final cost of ownership is determined by the availability and cost of tested-good-die in wafer form to fit the assembly infrastructure.
The stacked-package (SP) consists of stacked, pre-tested packages or a mix of tested-good-die and packages. Two types are emerging as favorites for stacking a DSP and memory for cell phone applications. Package-on-package (PoP) stacks a fully tested memory BGA on top of another BGA that contains the DSP. PoP interconnects the two devices with solder balls arranged in the periphery to clear the mold cap. Package-in-package (PiP) stacks fully tested memory LGA on top of a DSP that can be a bare die or packaged in a BGA. PiP interconnects both with wire bonding to mold into one standard BGA. The value of SPs is their higher final test yield compared to the equivalent SDP, though their footprint and profile are slightly larger. The final cost-of-ownership is determined by the trade-off of higher packaging cost for better final test yield and broader supply base. The packages to be stacked are conventional, but their design is tailored to the application and the type of interconnection. No two packages off the shelf can be stacked unless they are designed to be stacked. Therefore, standards are critical to the proliferation of stacked-packages.
The multi-package-module (MPM) combines stacking and side-by-side assembly of bare die, packages, and passives using wire bond, flip chip, and surface mount assembly in one BGA. The packages to be stacked are usually off the shelf, but the MPM footprint and profile is larger and has a significantly higher packaging cost than SDP or SP. Though the cost-of-ownership may be higher compared to conventional surface mount assembly on the motherboard, MPM’s value comes from higher performance achieved through the integration.
Traditionally, integration of all chips and other components is done on the product motherboard. System-on-chip (SoC) has been integrating many chips of compatible design and process into a single larger die, increasing performance and reducing overall footprint. This will continue, but will be limited by die size, die cost, incompatibility of chip design and process, IP integration, and chip complexity. 3-D packaging provides a complementary level of functional integration that can include chip designs and processes and other components that cannot be integrated in a SoC – without the IP integration issues. Digital, analog, memory and RF designs, and lower-cost SoCs, MEMs, and passives can be assembled in a small-footprint package that reduces complexity of the motherboard and frees space for new functions. Even products that are primarily cost-driven are exploring new applications using this technology to expand their market offerings, reduce their cost, and achieve better reliability because of the reduced number of connections. 3-D packaging today represents a growing level of functional integration that enables function design flexibility, lower cost, and shorter time-to-market using the established supply infrastructure.
Typically, a 3-D package includes chips from at least two suppliers, such as a DSP and memory. Assembly of the appropriate 3-D package can be done either by the IDM or the OEM. Typically, the IDM makes the DSP and buys the memory and can assemble both in a SDP or a PiP-like package. The OEM buys both the packaged DSP and memory and stacks them in a PoP-like package at the motherboard-assembly level. In either case, the choice of package type is determined not only by the needs of the final product, including footprint, profile, and cost, but by the business model of component procurement, assembly, and ownership of the final 3-D package.
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MARCOS KARNEZOS, Ph.D, chief technology officer, may be contacted at STATS ChipPAC, 47400 Kato Rd., Fremont, CA 94538; e-mail: [email protected].