IMEC develops high-performance 90nm CMOS platform for RF applications

July 25, 2005 – IMEC has developed a 90nm low-cost RF-CMOS platform targeting applications in the 5-24GHz range, according to IMEC’s July newsletter on this paper, which was presented at the 2005 VLSI Conference.

Above-IC layers were realized on top of IMEC’s 90nm CMOS baseline process to integrate high-Q inductors and interconnects. The platform shows enhanced analog/RF performances of both active and passive devices, assessed by a monolithic integrated 5GHz RF-CMOS low-noise amplifier (LNA) with highest ever-reported performance.

RF-CMOS technology is becoming increasingly important for RF applications well into the GHz range. The inherent low cost and high integration capabilities of CMOS technology make RF-CMOS a strong contender for traditional silicon bipolar solutions. Major concern is the quality of the integrated passives. They are the key technological differentiators that limit signal degradation and power consumption.

IMEC has developed a low-cost RF-CMOS platform based on its 90nm CMOS process. p-type 20W.cm Si substrates with 3 to 5 levels of metal, Cu/oxide back-end of line (BEOL) were used. The MOSFET has a minimum physical gate length of 65nm, with an effective oxide thickness of 1.5nm and a threshold voltage (VT) of 0.3V for the NMOS transistor. The NMOS performance could be improved by careful process tuning and layout optimization, demonstrated by the cut-off frequency (fT) and maximum oscillation frequency (fmax) of 170GHz and 240GHz respectively.

Thin-film wafer-level packaging (WLP) technology is realized on top of the passivation layer of this 90nm CMOS process as an above-IC approach to obtain high-quality (high-Q) inductors and interconnects. Integration of the inductors above the passivation layer reduces problems such as high sheet resistance (because of the on-chip metallization) and losses in the semiconducting silicon substrate, yielding higher Q factors and higher resonance frequencies. The WLP technology has alternating layers of 5 to 20 micron thick photo-benzo-cyclobutene (BCB) and electroplated cupper. Inductors are realized in a 5µm thick WLP Cu layer. A peak Q of [email protected] is measured for a symmetrical 2.7nH above-IC inductor. The Cu/Ni/Au top metal makes the flow compatible with the standard wire bonding technology.

In addition to the above-IC inductors, a portfolio of high-Q passive components, such as high-Q metal-insulator-metal (MIM) capacitors and MOS varactors, is available.
This approach resulted in an excellent performance of a monolithic 5GHz RF-CMOS LNA with inductive source degeneration. A very high gain of 18dB and a very low noise figure of 1.5dB have been achieved, for only 4.8mW power consumption.

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