Increased co-design needed to advance electronics miniaturization

July 22, 2005 – Semiconductor industry leaders gathered last week at the 2005 Electronic Product Miniaturization Symposium in San Francisco to share ideas and explore new technologies for designing next-generation electronic products. A number of innovative miniaturization and integration technologies, such as smart industrial design, semiconductor design tools, semiconductor packaging, and thermal analysis were explored.

However, despite the availability of many of these technologies, the consensus among the speakers was that the industry needs to improve design collaboration across the entire supply chain to fully realize the performance, portability and price advantages of component and system-level miniaturization.

Several presentations at the symposium focused on the miniaturization of mobile electronics, specifically cellular phones. While semiconductor packaging technologies such as chip-scale packaging (CSP) and multichip packaging (MCP) have driven the miniaturization of wireless products over the past several years, there is significant industry interest to further miniaturize and enhance the functionality of cellular phones. According to David Tuckerman, Tessera’s chief technical officer, these trends are leading to a new class of integrated electronic products, such as camcorder phones.

Tuckerman also illustrated how Moore’s Law has done a good job shrinking silicon, but stated that there is a lot more that can be done in the way of chip packaging and interconnect to further miniaturize systems and increase performance.

Also commenting on miniaturization in the wireless area were Tom Gregorich, senior director IC package engineering, Qualcomm, and Jon Kang, senior VP, technical marketing group, Samsung Semiconductor, who both provided insight into how semiconductor packaging has accelerated the evolution of mobile electronics. Gregorich explained how wireless semiconductor manufacturers are reducing the footprint and enhancing the performance of their products by leveraging system-in-package (SiP) technologies, such as a stacked die, stacked package and stacked module techniques. Kang echoed the importance of semiconductor packaging on driving the future of wireless applications. As an illustrative example, he cited a business traveler who can carry approximately 20 GBytes of data today (in the form of a laptop, smart phone, USB-drive, etc.), and by 2007, that same traveler is expected to carry 100 GBytes or more due to aggressive memory integration from suppliers.

In a separate presentation, Mark Christensen, principal consultant, Prismark Partners, LLC, predicted that multi-chip packages would increase from 500 million units shipped in 2003 to an estimated 2.1 billion units in 2009. In the area of RF packaging, Charles White, senior director, development and engineering at Tessera, provided insight into new SiP technologies that provide significant cost, performance and miniaturization advantages in wireless applications.

From the design tools perspective, Felicia James, VP, Virtuoso Platform, Cadence, discussed the work being done to develop electronic design tools that enable enhanced concurrent design and information exchange. James stressed the importance of being able to capture real-world effects early on in the design process, such as analyzing 3D effects in the context of the overall simulation. Echoing a key theme of the symposium, James stated that the choices designers make at the earliest stages of the design process have a profound impact on the rest of the design. As a result, increased co-design and knowledge sharing is required to further improve electronics miniaturization and integration. The symposium was organized by Tessera Technologies Inc.


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