Soluris, CEA-Leti form JDP on sub-45nm logic technologies

July 6, 2005 – Soluris and CEA-Leti have announced that they have engaged a joint development program (JDP) involving Soluris’ Yosemite SP-1000 CD-SEM to help characterize the sub-45nm logic technologies at CEA-Leti’s new Minatec research facility in Grenoble, France.

Key to the agreement is the Yosemite’s implementation of critical shape metrology, a physics-based modeling algorithm, to extract three-dimensional shape information from the CD-SEM signal.

“As a source of innovation and technology transfer for the global semiconductor industry, we need[ed] a metrology tool providing a high accurate measurement data on sub-45nm technologies,” said Patrick Dussouillez, head of the Silicon Platform Division at CEA-Leti.

“This JDP with CEA-Leti is truly a win-win for both parties,” adds Robert Ricau, Soluris’ European VP of operations. “Using the Yosemite CD-SEM, CEA-Leti will obtain the information needed to develop next-generation technologies, and Soluris will gain insight into the metrology requirements that will be needed at the 65nm, 45nm, and even 32nm process nodes.”


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