MOSAID, UMC to develop memory controller IP for 90nm, 130nm

August 11, 2005 – MOSAID Technologies Inc. and foundry UMC have announced that they are cooperating on the development of comprehensive double data rate (DDR)/DDR2 SDRAM memory controller semiconductor intellectual property solutions for UMC’s 90nm and 130nm process geometries, according to Canada Newswire English.

The MOSAID DDR/DDR2 SDRAM memory controller IP is slated to be available starting in the fall.

The comprehensive MOSAID memory controller solution, for UMC’s advanced processes, is being built with high performance SSTL I/O library and delay locked loop (DLL) hardened IP elements as well as the controller RTL soft IP. The solution supports both the DDR SDRAM standard with SSTL2 signaling and DDR2 SDRAM with SSTL18 signaling.

It is also being designed so customers’ products can interface to either DDR SDRAM or DDR2 SDRAM without requiring two separately manufactured versions of the product. The MOSAID memory controller IP will be delivered as a library of easily connected elements rather than a single, hardened block. This will allow customers the flexibility to create a variety of different memory interface and bond pad configurations. The controller is intended to support chip-to-chip and chip-to-module configurations with speeds up to 800Mb/s/pin.


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