As device manufacturing continues down the path of smaller geometries and increased densities laid out by Moore’s law, the importance of packaging technology to the overall performance of the device continues to grow in parallel. In recent years, this has manifested itself in the growth of flip chip or “bump” packaging and 3D or stacked packages, as well as other wafer-level packaging or integrated substrate technologies. These shifts in package types and technologies are being driven by the need for increased device performance, higher data rates, and increased functionality in today’s high-end consumer electronic and computing applications. To enable these high-performance devices, and consequently reap the rewards of higher margin products, the move toward more complex wafer-level processing in the traditional back-end semiconductor assembly and test arena has increased in the last 5 years.
Historically, the front-end semiconductor process ended with the completion of the wafer fabrication process and the application of the final passivation and metal layers on the IC. The next set of back-end processes, which had long been relegated to semiconductor assembly and test providers, was often overlooked as being non-critical to the performance of the device. Today, the distinction between the back end and front end is not so clear, nor are the device designers and semiconductor manufacturers taking for granted the contribution of the package to the overall device performance or application. In a growing number of consumer electronics applications, it is the package, not the IC, that is the critical enabling aspect of the technology. The industry is experiencing a new dynamic with a convergence of front-end wafer processing and back-end assembly, and with this, a whole new set of opportunities and challenges has presented itself to the semiconductor assembly and test providers.
This move toward wafer-level processing necessitates a new level of involvement by the back-end assembly and test community. Initial forays into wafer-level processing by back-end providers took the form of licensed solder or gold bump processes. While this represented large technical and commercial investments, those semiconductor assembly and test providers that embraced wafer-level processing early on are now reaping the rewards of their foresight. The development of a new wafer-savvy semiconductor assembly and test community has created a desire to continue the growth in these high value-add processes. Concurrently, the growth in high-end consumer electronics and ensuing need for form-factor reduction, reduced power consumption, and wireless capability have created new requirements in wafer-level package design and processing. Unlike front-end manufacturing where line width and transistor performance drive technology development, wafer-level processing for packaging focuses on electrical performance, aspect-ratio performance, and thermal stability.
While the semiconductor assembly and test providers continue to see growth in solder and gold bump demand, recently there has been a growing need to support system-level integration via wafer-level processing. This has taking the form of both system-in-package applications as well as increased on-chip functionality required for system-on-chip applications. This represents additional challenges in the form of increased package design complexity, and additional wafer-level technical challenges to accommodate the need driven by 3D integration and improved packaging performance. In terms of wafer-level processing requirements, the addition of post passivation wiring levels and on-chip or on-substrate passive components as well as through-hole via stacking and wafer-to-wafer bonding has created new opportunities for those with wafer-level processing capability. This need has been embraced quickly by the semiconductor assembly and test community as a way to provide product differentiation.
The increased use of wafer-level processing technologies driven by the growing complexity of today’s high-end packages has ushered in a new level of technology in semiconductor assembly and test. Therefore, what is needed is new processes to support the unique requirements of wafer-level processing for packaging. It is with the mastering of these new challenges that the semiconductor assembly and test community will continue to improve package performance. The passivation layer is no longer the last step in the semiconductor wafer-fab process. Advanced packaging technologies, enabled by the development of wafer-level processes, have shifted the value proposition in semiconductor manufacturing. With the development of these new packaging technologies, the semiconductor assembly and test providers have become technology enablers for the next generation of consumer electronics and computing applications.
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STEPHEN KAY, director of advanced packaging technology, may be contacted at Ultratech Inc., San Jose, CA 95052; 408/325-6067; e-mail: [email protected].