October 3, 2005 – Brion Technologies has announced a joint development agreement with STMicroelectronics, Philips Semiconductors, and Freescale Semiconductor, R&D partners in the Crolles2 Alliance. Brion has delivered RET/OPC process window-enabled applications that run on the company’s hardware-accelerated Tachyon platform.
The Crolles2 Alliance partners and Brion intend to further test and develop these applications, checking and maximizing the lithography manufacturability for chip designs. Comprehensive model-based simulations of multiple focus and exposure conditions are used to enable larger process windows for advanced manufacturing by avoiding yield-limiting lithography “hot spots.”
The three companies have also entered into licenses for Brion’s Tachyon RDI product. The system was recently installed in the Crolles2 pilot facility and is expected to be deployed in a production environment for 90nm and 65nm designs and beyond. The RDI system runs full-chip model-based RET Design Inspection, which has rapidly become an essential production requirement for 110 nm and below processes.
Brion’s Tachyon platform is a hybrid architecture that combines the strengths of image-based simulation with the polygon- and contour-based geometry processing used by conventional EDA tools for physical design.
Under a five-year agreement extending through to December 2007, the Crolles2 Alliance brings together STMicroelectronics, Philips and Freescale Semiconductor, Inc., in an alliance. Their joint Crolles2 center is focusing on specific CMOS technologies at the forefront of semiconductor R&D, including design platform and packaging. The Alliance is currently running 90nm in production, 65nm for prototyping and continues developing CMOS processes at 45nm and, ultimately, the 32nm node.