October 5, 2005 – KLA-Tencor has formally unveiled DesignScan, the industry’s first full-chip process window inspection system for post-RET (resolution enhancement technology) reticle design layout inspection. DesignScan enables chipmakers to reduce the number of mask design respins needed to achieve a high-yielding design, resulting in better parametric design performance and faster time-to-market.
Leveraging DesignScan, design-related performance and yield-limiting patterns can be identified and optimized before committing the design to mask production. DesignScan is especially suited for 90nm and below designs, where lithography process windows are extremely small and problematic. Several leading integrated device manufactures (IDMs), foundry, and fabless chipmakers are currently evaluating DesignScan.
DesignScan enables inline inspection of post-RET reticle designs for errors through the process window. Along with LithoView, a new capability specifically developed to enhance collaboration between foundries and fabless chipmakers, DesignScan identifies performance and yield-detracting patterns and facilitates the communication of this information upstream to the fabless design community.
LithoView enables fabless designers to view the inspection results obtained by DesignScan. DesignScan enables the performance of the design through the process window to be improved by optimizing the design for the wafer lithography process, optimizing the post-RET reticle layout for the lithography process, or optimizing the lithography process for the design.
“Design-for-manufacturing (DFM) is an issue of ever-greater importance as mask layouts deviate further and further away from designer intent,” stated Harold Lehon, GM of KLA-Tencor’s Reticle and Photomask Inspection Division (RAPID). “As a company dedicated to yield management, KLA-Tencor is committed to enabling companies to make better decisions and improve their yields at all levels of the semiconductor value chain. With solutions like DesignScan, we’re able to move our yield knowledge and expertise upstream to the post-RET design stage.”
Lithography today requires the addition of extremely complex RETs, such as OPC features, to mask layouts in order to achieve successful patterning. After OPC is added to the design, it must be inspected to ensure it is free of design errors that can lead to patterned defects, as well as to ensure it provides a reasonable process window for a specific design in a given process, before the mask is made.
Detecting these errors as early as possible is critical, since a design error found before mask production may take a few days or a week to correct, yet an error that goes unchecked until wafer inspection in the fab can result in one or more months of cycle time delay. DesignScan offers the fastest turnaround time for process window inspection and optimization.