Oki Electric develops transistor that reduces power consumption by >90%

October 7, 2005 – Oki Electric Industry Co. Ltd. has announced the development of SOI (Silicon on Insulator)-CMOS, a new device structure for super low off-leakage current. While maintaining the speed of performance of previous devices, this transistor reduces the standby consumption current (off-leak current) by over 90% compared to previous transistors. Oki claims to be the first company to develop a fully depleted SOI transistor using a non-doped body and non-overlap type SOI structure.

“With growth in the use of personal and mobile communication products, demands for lower power consumption LSIs have also been increasing. To respond to such needs we have been researching and developing the fully depleted SOI technology, which enables a high performance, low power consumption LSI,” said Akira Kamo, president of the Silicon Solutions Company at Oki Electric. “We are excited at this experimental stage achievement. Confirming high-speed performance while significantly reducing off-leakage current enables us to accelerate development in sensor network products using coin batteries and solar power going forward.”

The newly developed non-doped body and non-overlap SOI structure made the following achievements:

1. In previous SOI devices, it was difficult to prevent current leakage because the body potential rises unless the electrical potential of the body were fixed. By achieving a non-doped structure, Oki succeeded in reducing the current leakage.

2. With the previous source/drain to gate overlapped structure, parasitic capacitance occurred at overlap regions, which reduced the performance speed. By achieving a non-overlap structure, Oki reduced unnecessary parasitic capacitance and improved performance speed.

To achieve a high threshold voltage for super low off-leakage current, it is common to use a process development based on gate electrode material different from conventional polysilicon, such as a metal gate electrode. However, as the process becomes more complex, the cost becomes higher. The new structure device uses P+ gate for NMOS, N+ gate for PMOS, the opposite in polarity of normal CMOS gates, thus increasing compatibility with conventional processes by using a low-cost polysilicon gate process, while also achieving a low-cost structure.

The non-overlap type structure transistor has been seen in bulk device used in high-speed, high-performance applications, but the Oki development is the first in the world using SOI for super low off-leak applications


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.