November 22, 2005 – AmberWave Systems Corp., a developer of strained silicon technology, today announced an advance in strained-silicon-on-insulator (SSOI) quality and manufacturability.
Counterintuitively, AmberWave significantly improved the end quality of the SSOI substrate by starting with a silicon substrate intentionally laden with “threading” defects. The presence of these initial “threading” defects – generally acceptable in limited numbers – reduces both the number of “threading” defects in the final substrate by one order of magnitude and “dislocation pileups” in the final substrate by as much as three orders of magnitude. Dislocation pile-ups are a different type of defect which, in contrast to threading defects, are significant impediments to device performance and yield.
The research is the result of collaboration between Dr. Matthew Erdtmann and Dr. Matthew Currie of AmberWave and David Black and Joseph Woicik from the National Institute of Standards and Technology (NIST). Their findings will be presented on December 1 at the 2005 Materials Research Society (MRS) Fall Meeting held in Boston, MA.
Dr. Erdtmann will also chair the MRS Meeting Session 12 focusing on “Progress in Semiconductor Materials V – Novel Materials and Electronic and Optoelectronic Applications.”
In addition to the quality improvement, this process also can be accomplished with a thinner strained silicon substrate, thereby significantly reducing growth time – the largest factor in fabrication expense. AmberWave’s research demonstrated growth times of less than five minutes per wafer.