A wafer-handling robot upgrade results in reduced wafer scratches

Dennis Winters, Samsung Austin Semiconductor LP, and Richard Kent, Fabworx Solutions Inc.

Fabs operating cluster tools from the 1990s frequently report robot-related wafer scratching as a common source of yield loss. When scratching occurs, the probability of killing a die is nearly 100%. The dominant cause of wafer scratching in these tools is robot droop, a result of wear that causes the robot blade to use more of the vertical clearance between the wafers within a cassette.

Faced with the probability of robot droop, a 200mm memory fab analyzed defect data to identify scratching in a set of tools. After evaluating options, the fab installed a robot upgrade that eliminated scratching and resulted in a payback on investment from higher yields within 10 weeks. Tool productivity also increased by 15% or more.

At the core of widely used manufacturing cluster tools are the wafer-handling robots, which, when introduced in the early 1990s, were considered state-of-the art. Over time, however, the OEM robot limitations have resulted in reduced tool productivity and yield. Among the potential problems are robot-induced particles generated by wafers sliding on the blade and exposed stainless steel bearings in the hub, elbow, and wrist assemblies. The slower operating speed of older robots also presents issues, as well as inaccurate placement of wafers due to sliding and imprecision in the robot arm joints. Tool downtime and parts costs often become con-cerns as robots age in volume manufacturing applications.

At the Samsung Austin Semiconductor fab, an effort was initiated to reduce scratch-related defects when a yield loss was identifed on three PVD cluster tools. Many of Samsung’s scratching incidents affected a random num-ber of die and wafers within a production lot. Defect data was collected on several of these incidents, and tool-induced scratches were extracted from other yield-limiting events reported. This analysis identified a common signature that was highly repeatable in both its orientation and on-wafer location.

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If you have any questions or comments, please contact: Julie MacShane, Managing Editor, SST at email: [email protected]


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