By Ed Korczynski, Senior Technical Editor
The ISMI Symposium on Manufacturing Effectiveness in Austin, TX, in October provided insights into the near future of high-volume semiconductor manufacturing. With fabs ramping 90nm and 65nm node processes, new mindsets and techniques are needed to manage the inherent complexity of manufacturing nanometer-scale IC structures.
Paul Farrar, IBM VP of semiconductor process development, provided some concrete examples of the limits of “classical scaling” in a keynote address. Fabs must now manage “nonstatistical” material and device behaviors – meaning that the physical length scales involved are so small as to preclude the use of statistics. For example, the traditional CMOS transistor gate dielectric that is already only ~2.4 nm thick will be 1.2nm thick, and with thickness now measured in terms of atomic layers, any atomic-level fluctuations have dramatic consequences. Dopant concentration fluctuations on the atomic scale are also now meaningful. “With 1000 atoms you could afford variations, but with 10 atoms you can’t afford any variation,” he said.
Another ramification of the limits of classic scaling is that even basic transistor performance improvement is no longer dominated by scaling. Down to the 180nm node, over 90% of performance improvement/node came from scaling, dropping only to ~85% at 130nm. However, for the 90nm “CMOS10S” process, IBM saw scaling account for <45% of performance improvement, and it expects <40% gain at 65nm. Innovation now dominates transistor performance increases, which implies that scheduled innovation is now the majority component in all technology plans.
An example of the innovation used at 90nm is the change from a single-tensile liner nitride layer to a dual-stress liner to induce opposite strains in PMOS and NMOS regions. The additional process complexity creates transistors with increased carrier mobility, resulting in >8% improvement in F
Innovation of this sort relies upon adding more unit processes to process modules, even though the time through each process-module needs to at least stay the same – if not improve – so that fabs can economically manufacture ICs. Consequently, throughputs and other fundamental unit-process metrics must improve so that a given process module’s cycle time can remain relatively constant. Interdependencies between unit processes within a changing process module are likely to induce new failure mechanisms, which in turn will challenge yield modeling and ramping of real silicon.
All of this additional complexity requires additional resources to manage, which explains why nearly all nanometer-era process development is being conducted by clusters of partners. IBM worked with a team of partners to rollout their mutual 90nm node technology into multiple fabs at multiple companies. Recently announced products using this technology include the Cell processor and the upcoming second generation Microsoft game console. There’s another metric for success in partnering, according to Farrar: limit the number of your partners to six. “Managing six partners – and I don’t mean to imply that we merely manage them since they also manage us – is difficult, so I wouldn’t recommend more.” — E.K.