IEDM Conference news

December 6, 2005 – At the International Electron Devices meeting this week in Washington, DC, news includes: 1) Limited and Fujitsu Laboratories Ltd. have developed carbon nanotube-based heatsinks for semiconductor chips. 2) Freescale Semiconductor has demonstrated a transistor that overcomes many of the challenges associated with vertical multigate devices. 3) STMicrolectronics unveiled a 65nm NOR Flash technology with a small cell size of 0.042 sq microns.

1) Limited and Fujitsu Laboratories Ltd. have succeeded in the development of carbon nanotube-based heatsinks for semiconductor chips. The use of carbon nanotubes as heatsinks for high-frequency high power amplifiers achieves heat dissipation and high amplification simultaneously.

The new technology represents a major step forward in developing practical applications that take advantage of the superior thermal conductivity of carbon nanotubes. It also enables the realization of high-performance amplifiers with high frequency and high power for next-generation mobile communication systems. This research is part of the Advanced Nanocarbon Application Project consigned to the Japan Fine Ceramics Center, by Japan’s New Energy and Industrial Technology Development Organization (NEDO).

2) Freescale Semiconductor has demonstrated a transistor that overcomes many of the design and manufacturing challenges associated with vertical multi-gate devices. The invention, called the Inverted T channel-field effect transistor (ITFET) device, features a combination of vertical and planar thin body structures within a single transistor.

By combining the stability and manufacturability of planar devices with the low leakage and other benefits of vertical devices, Freescale’s ITFET bridges the debate on planar versus vertical CMOS devices and offers key advantages of both technologies in a single device.

3) STMicroelectronics will present a 65 nm NOR Flash technology with the smallest cell size of 0.042 square micron and a novel HBT (heterojunction bipolar transistor) architecture for high-performance 1-bit/cell and 2-bit/cell products. ST’s approach utilizes cobalt salicide and three copper metallization layers to integrate the 65nm NOR Flash array with low-voltage CMOS logic for 1.8 V applications.

Another two contributions at IEDM from ST deal with the important aspects of scaling and reliability in nonvolatile memory structures. A paper co-authored by research partners at the Polytechnic of Milan, reveals a new experimental technique for investigating stress-induced defects in the silicon oxide, while the second paper, co-authored by ST, CEA-LETI, the University of Pisa, and CNRS, describes a study of electrical behavior in discrete-trap nonvolatile memories during data retention and its impact on cell-scaling.

Together with Philips and Freescale, ST will co-present at IEDM 2005 the latest achievements of the joint research teams working within the Crolles2 Alliance.


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