NEC unveils 45nm work on LSI interconnect, sub-10nm transistors

December 8, 2005 – NEC Corp. and NEC Electronics Corp. said they have developed a new device technology for low-power, high-performance system LSI capable of enhancing functionality of sub-10nm transistors.

The work involved creating a new elevated source/drain extension (SDE) structure through silicon selective-epitaxial growth technique, decreasing juction depth and reducing parasitic resistance and enhancing on-current. Also, the thickness of the elevated SDE can be self-aligned and controlled by applying a tunneling epitaxial growth technique to the gap region, (created by a selective etching technique) between the silicon surface and sidewall material. Test fabrications carried out by NEC on 6nm transistors demonstrate the new technology simultaneously achieves controlled elevation fo the source-drain region and significantly improves on-off ratio, and suggest system-on-silicon LSI can be advanced through 2020 using low-cost planar bulk technology.

Meanwhile, NEC also said it has made advancements in developing 45nm-node LSI interconnect technology. Better reliability was achieved through a special oxygen absorption process on low-oxygen-content copper alloy, and combining intensively thinned dual-damascene structures with a new molecular-pore-stacked (MPS low-k film (k=2.4) achieves 24% reduction in power consumption vs. 65nm interconnect. The technology is seen enabling a 50% reduction in chip size and more than 20% overall reduction in power consumption for 45nm-node CMOS transistors vs. 65nm-node devices.


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