Analysis indicates new direction for Intel’s 65nm process

January 24, 2006 – A firm’s inspection of Intel’s 65nm logic process indicates an “innovative and radical shift” in focus from scaling physical dimensions toward the promises of strain engineering.

Using transmission and scanning electron microscope (TEM and SEM) analysis, Semiconductor Insights, Kanata, Ontario, Canada, inspected the structure and core transistor characterization of Intel’s 65nm Pentium D 920 dual-core processor, the low-end model of its recently-released 65nm mobile dual core processor, with 2.80GHz clock speed, 2x2MB L2 cache, 2.80GHz clock speed, and 800MHz front-side bus. What it found was evidence of a new direction in focus toward increasing channel strain and enhancing carrier mobilities, instead of scaling physical dimensions. The firm also determined that the chip incorporates a new SRAM layout optimized for density with dimensions “slightly relaxed” from the chipmaker’s published data on its SRAM test chip.

Focusing on channel strain and carrier mobilities “avoids the leakage and reliability challenges involved with scaling down the gate oxide thickness or with introducing a new class of materials into the dielectric,” noted Don Scansen, process technology manager for SI. “It is clear that strain technology is delivering on its promise at Intel.”

SI also is looking at other features of the 65nm chip, including dimensions for minimum via/contacts, gate spacing/lengths, gate dielectric; the SiGe source/drain for PFET including Ge concentration gradient; an analysis of new silicide processing to enable ultrashallow junctions; and scanning capacitance analysis of ultrashallow junctions.


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