By Chris Edwards, Contributing Editor, Europe
Amid the growing clamor of companies seeking to address the interface between electronic design automation and manufacturing, a group of European startups is leveraging close links with local chipmakers to develop design-for-manufacturing (DFM) tools that let designers tackle the increasing problem of process variation and other systematic yield issues. Although Europe’s IDMs remain the prime focus for these DFM startups, the market is expanding as foundries and their fabless customers become more aware of the impact that design-related problems have on yield in sub-100nm processes.
Xyalis, based in Grenoble, France, is adapting its technology to predict the effects of chemical-mechanical polishing (CMP) on metal layers to better deal with the problems faced by fabless chipmakers as well as by foundries struggling to improve yield on new processes. The current version of the company’s GTSmooth tool, which was put through trials at STMicroelectronics’ fabs several years ago, inserts dummy metal elements to improve the planarity of metal layers post-CMP. It needs destructive testing of complete test wafers in combination with a good model of CMP behavior to provide accurate estimates for new designs.
Eric Beisser, CEO of Xyalis, said customers may not have enough experience with a process to develop an accurate model, or in the case of fabless companies, do not have funds to run extensive tests at the foundry. “We are proposing an approach in which the customer works directly from the chips they are producing. We provide to the customer a set of significant points within the design that are suitable for calibration and derive a model from that,” he said. “At the moment, we provide that as a service, but we are working on a tool to do it.”
Beisser added that the approach will be more responsive than the existing method, whereby it can take up to six months to process the data, by which time the process may have moved on. “With this new approach, each time the customer has a new design, we can re-analyze it and follow very closely changes in the process,” he said.
Also in Grenoble, Infiniscale Technologies, a much younger startup, aims to bring improved design-for-yield prediction to analog and mixed-signal chips. Firas Mohamed, the company’s CEO, and his team of four have developed a technology they claim greatly simplifies the process of creating analog models that take into account process factors based on the parametric-yield data provided by foundries. Working with STMicroelectronics to prove its technology, the company targets a synthesis tool by 3Q06 that will be able to center an analog circuit for best yield based on process parameters. “And it will predict the evolution of the process over a number of generations,” added Firas.
Other DFM startups are working with European IDMs to develop their tools. Edinburgh, Scotland-based Predictions Software Ltd.’s Eyes tool was first used industrially by STMicroelectronics in the late 1990s. Elsewhere, Germany’s Muneda GmbH, a spinout from the Technical U. of Munich, has developed close links to Infineon Technologies AG, working with the chipmaker as part of a European Union-funded project to prove its approach for improving the yield of analog circuits.
While the yield data itself is not often provided to the tool vendors in the secretive world of DFM — the IDMs create their own databases and keep the data to themselves — the users do provide feedback on what they need. “We don’t need to know anything about their processes,” said Gerard Allen, founder and CEO of Predictions, a spinout from U. of Edinburgh. “However, you can see from requests that come in from IDMs what their main concerns are. We have had requests for things to look at, such as redundant vias.” — Chris Edwards, Contributing Editor, Europe