SUSS Names Executive Versed in MEMS and Opens Training Facilities in Munich
 Amir R. Mirza, Ph.D. |
MUNICH, GERMANY – SUSS MicroTec recently appointed Amir R. Mirza, Ph.D., a MEMS industry veteran, as International Product Manager at its Waterbury, VT-based Wafer Bonding Division. Mirza’s extensive MEMS experience spans the development of various silicon micromachined products such as accelerometers, pressure sensors, optical MEMS, and microfluidic devices. He has held engineering and management positions with Honeywell, Motorola, and GE, where he served as Director of Advanced Technologies. In that position, he was responsible for R&D for both MEMS design and process development.
Mirza also brings years of semiconductor capital equipment experience, most recently from Santa Barbara, CA-based Innovative Micro Technology, a MEMS design and fabrication foundry, where he held program management responsibilities for new products. “We are delighted to have someone of Dr. Mirza’s caliber and strong semiconductor industry experience to spearhead our wafer bonding business. Wafer bonding is a strategic growth opportunity for SUSS MicroTec, and having experienced product leadership is key to expanding our position in the marketplace,” states Michael Kipp, general manager for SUSS’s Wafer Bonding Division.
SUSS also opened new product training facilities at its Munich, Germany, headquarters to meet operator and maintenance training demand for SUSS’s precision lithography systems. At the new facilities, prospective operators, process engineers, and service personnel receive instructions on setup, operation, adjustment, and service of SUSS’s mask aligners and coaters, including troubleshooting and maintenance. Two full-time training specialists and appointed product and process engineers are on site to ensure that users will get full benefit from such systems. “A profitable partnership with our customers based on successful transfer of our know-how helps them to better understand and master the sophisticated and complex technology of SUSS machines,” explains Frank Runkel, application and training manager of SUSS’s Lithography Division.
INSIGHTS FROM MEPTEC
 BY JULIA GOLDSTEIN |
SAN JOSE, CA – Device manufacturers and OEMs shared their insights with the packaging industry at MEPTEC’s November symposium, “Roadmaps for the Next Generation of Semiconductor Packaging.” Co-design and co-development was the overlying theme. It will take circuit designers, package designers, and manufacturers working together to produce a successful product in the shortest amount of time.
“If we solve issues together, we get business together,” noted Sergio Camerlo of Cisco. Nikhil Kelkar of Intersil stressed that there is only one chance to be successful in launching a product, and product/package co-design is important for success. Tarun Verma of Altera explained that package development is often done in a “virtual world,” months before first silicon.
Co-development also needs to extend to the board level, because packages need to be optimized for board layout. High-density substrates enable fine pitch within a package, but for PCBs, the array pitch remains at 1 mm, slowing the drive toward miniaturization, according to Camerlo. Keith Newman of Sun Microsystems stated that reduction to 0.8 mm is not planned because of cost and manufacturing limitations.
Consolidation will occur among equipment manufacturers, warned Bob Johnson of Gartner Dataquest. He predicted that within 10 years, fewer than 10 suppliers will produce 80% of manufacturing equipment. Johnson expects a handful of test and assembly equipment suppliers to survive, and the possibility exists for companies like Applied Materials and KLA-Tencor to expand into back-end equipment. He stressed the importance of consortia between device and equipment manufacturers and advised the packaging industry to follow the front-end in forming consortia to share R&D costs.
Bo Chang of Cypress showed trends in package types over the last few years in a chart he called “Sunrise, sunset.” QFN packages are on the rise at Cypress, as are stacked BGAs. Newman displayed a similar chart, adopting Chang’s analogy. Newman’s chart predicts a “sunset” for wire-bonded packages for ASICs in 2006, but he noted that in the past he had predicted zero wire-bonded packages within a year. However, wire-bonded array packages made up 20% of Sun’s ASIC packages in 2004 and 2005, following a trend toward organic packages. Microprocessor packages at Sun are primarily ceramic and have been entirely flip chip since 1996.
Package stacking can be difficult to implement and is not a drop-in solution, noted Matt Kaufmann of Broadcom, addressing specific challenges for RF packaging. He lamented the lack of consistency and standards among suppliers. The existence of so many different processes and materials sets makes evaluating suppliers difficult. RF-specific challenges include coupling between package circuitry and the device – such interactions can make an inductor function like a capacitor. Power management and shield are also becoming critical with the trend toward more functionality in a chip, and with chip-on-board approaches replacing modules in mobile RF devices.
New Nanowire Fabrication Technologies Available
BUFFALO, NY – NanoDynamics Inc. will commercialize new nanowire fabrication technologies developed by Nano Cluster Devices Ltd., its New Zealand-based partner. U.S.-based Nano Cluster Devices Inc., which has been granted a license, will drive its commercialization, allowing a number of patent-pending technologies to be brought to market, and providing a platform for commercializing nanoscale electronic devices and semiconductors.
Nano Cluster Devices’ technology mixes the positive aspects of both “top-down” and “bottom-up” manufacturing methods, enabling highly controllable, self-assembled atomic clusters to achieve faster, more precise semiconductor fabrication.
“Atomic clusters exhibit a range of useful electrical, chemical, and magnetic properties, demonstrating great potential as the building blocks of nanoscale electronic and complex semiconductor devices,” claims Dr. Simon Brown, chief scientist at Nano Cluster Devices. “This nanotechnology enables the electronics industry to make advanced devices and components; products that are already technologically proven, but have yet to be brought to market because of manufacturing difficulties.”
“In order to make nanotechnology commercially viable, it’s necessary to develop practical means of application that fits within the existing infrastructure of the semiconductor manufacturing industry,” adds Keith Blakely, NanoDynamics’ CEO.
Some of the technology’s key developments in the past year include a more sensitive and economic hydrogen sensor prototype; technology to produce highly precise conductive wire patterns while eliminating the “lift-off” process step; a process that causes atomic clusters of conductive material to fall into a V-groove and then self-weld to create a conductive wire; and a cluster assembly process based on stenciling or “shadow-mask” techniques that eliminates clogging problems when the material is applied through the stencil. Nano Cluster Devices can now deliver a stenciling technology where nanoclusters are used to build narrow wires without agglomerating or clogging the stencil.