SiC firm licenses Penn St. CVD polishing process

January 19, 2006 – Intrinsic Semiconductor Corp., Dulles, VA, has licensed an advanced chemical-mechanical polishing (ACMP) process for silicon carbide (SiC) wafers, created at Penn St.’s Electro-Optics Center through funding by the Defense Advanced Research Projects Agency (DARPA).

The process, which eliminates the selectivity associated with the removal of material surrounding scratches and defects, has been shown to create atomically flat surfaces for epitaxial device layers better than available with current processes.

Details provided at last fall’s International Conference on Silicon Carbide and Related Materials indicated material removal rates of >150nm/hr on 50mm wafers, with total dislocation densities of (<1x10[+]6 dislocations/cm[+]2), on the order of the densities reported for the best as grown silicon carbide crystals, with GaN HEMT layer characterization indicating electrical performance meeting or exceeding industry requirements.

Intrinsic is in the process of moving its 50mm-75mm SiC and GaN epitaxial products, and other SiC substrates, to 100mm.

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