January 25, 2006 – Japanese industry consortium Semiconductor Technology Academic Research Center (STARC) has announced programs with Mentor Graphics Corp. and FishTail Design Automation to develop at-speed delay test methodologies for IC designs, and improve production flow for chip implementation.
The work will involve incorporating technologies into Mentor Graphics’ automated test pattern generation IC test tools. “As our member companies move to 90 and 65nm technologies, improving manufacturing test is a critical requirement,” stated Tasuo Sato, senior manager, test methodology, STARC.
Meanwhile, STARC also is developing a new production flow for chip implementation using timing exception generation technology from FishTail Design Automation Inc. On a 500K gate microprocessor design from one of STARC’s member companies, the new flow reduced total negative slack from 70ns to 33ns.
“The pain experienced by chip-implementation engineers in trying to get a chip to timing closure while working with an incomplete constraint set is real and recurring,” noted Ajay Daga, founder and CEO of FishTail. STARC VP and GM Nobuyuki Nishiguchi noted that “the use of FishTail exceptions in the chip-implementation flow will provide substantial improvement in design quality of results and turnaround time.”