3-D-stacked ICs with Copper Nails

Allows System Size Reduction


Extreme miniaturization of electronic systems requires innovative interconnection and packaging technologies that overcome the limitations imposed by 2-D planar architectures. 3-D integration allows system-size reduction in area and volume, improving packaging density for applications such as handheld products. 3-D integration improves performance because interconnects in a 3-D assembly are shorter than in a 2-D configuration, allowing for a higher operating speed and smaller power consumption. This offers the possibility of stacking devices produced with different technologies; an obvious choice for many sensor applications, which use specific substrate materials that are incompatible with Si-CMOS processing. The combination of logic and memory circuits is another application that benefits from a 3-D approach. Classical 2-D interconnects between logic and memory dies result in slow and power-hungry interconnects, or – in a 2-D system-on-chip (SoC) configuration – consume too much die area. A 3-D interconnect technology may solve this problem by allowing for logic “tiles” on a first die to access memory banks on a memory chip directly on top of it.

Many handheld products already contain 3-D-stacked dies connected to each other and the package by peripheral wire bonds. Up to 5 functional dies can be stacked in a single package. However, this type of stacked-IC package has limitations. Besides a low wiring density and long wire bonds, the technique does not allow for area-array contacts to the die. In addition, stacked-die packages require known good dies (KGD) to avoid compound yield problems. This requirement introduces additional costs, making the stack more expensive (Figure 1).

Figure 1. BGA package with multiple stacked die and wire-bond interconnects.
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3-D-stacked IC for Very High Density

Advanced systems and scaled semiconductor devices need an innovative 3-D packaging and interconnection solution. This technology should allow for high-density 3-D interconnects; have shorter interconnects with low parasitic capacitance for high-speed and low-power applications; have minimal impact on the front-end-of-line (FEOL) and the back-end-of-line (BEOL); allow for different die sizes, and handle the KGD problem with a method that sorts out the dies, favoring die-to-wafer 3-D stacking. It should consider the thermal management of the 3-D stack and offer a cost-effective solution. 3-D technology should be chosen to fit requirements set forth by the application.

Different technology solutions can be categorized according to the platform used to create the 3-D interconnect structures. In a 3-D-system-in-package (SiP) technology, the traditional packaging infrastructure is used to create 3-D packages. This technology encompasses wire-bond die stacks and package-on-package 3-D stacks, and is characterized by a low interconnect density. A particular application area is the stacking of sub-system SiP packages to realize true ambient intelligence systems.

The 3-D wafer-level packaging (WLP) technology is based on the WLP infrastructure used for flip chip bumping and redistribution metallizations at wafer-level. It achieves higher integration densities than 3-D-SiP, and allows for the direct interconnection between circuit blocks, or “tiles” of the different die, rather than through traditional IC-bonding pads. By using collective wafer-level processing, this technology is more cost-effective for achieving higher integration densities.

The highest interconnect density is obtained with the 3-D-stacked IC (3-D-SIC) approach. 3-D-SIC uses Si-foundry technology to realize through-Si via connections with a very high density. One may envisage 3-D interconnects at the lowest interconnect level – the transistors themselves (local BEOL wiring hierarchy). This requires an extremely high 3-D wiring density. The concept can also be applied to interconnect large circuit blocks (tiles). In this 3-D-SoC approach to 3-D-SiC, 3-D interconnects correspond to global and intermediate BEOL on-chip interconnects.

Several technologies still in the R&D phase are being developed; most of them realizing the through-vias after finalizing the IC process. One company* proposes a different approach to generate 3-D-stacked ICs. Cu vias are realized in a single damascene process performed after front-end and contact processing, prior to processing back-end metallization layers.

3-D-SIC with Cu Nail

The 3-D-SIC concept introduces a small Si via and Cu plug – the Cu nail, which is processed after the FEOL process (transistors), but before the BEOL process (multilayer damascene interconnect layers). In its first embodiment, the Cu nail is realized by plasma etching a ±15-µm-deep Si hole with a diameter of 3 to 5 µm. A modified Cu single damascene process is applied to fill the hole. A CVD oxide layer is used as a thin dielectric insulating layer and as a CMP stop layer, followed by the deposition of a TaN barrier. The via hole is then filled with electroplated copper. CMP is used to remove the Cu “overburden.” After this process, standard BEOL processing finalizes the Si die.

Next, the wafer is mounted on a temporary carrier and thinned down to a Si thickness of 10 µm. In the process, the Cu nails are exposed on the wafer backside.

Figure 2. Schematic representation of the 3-D-SIC Cu-nail via process. Left: standard CMOS wafer with Cu nail before the BEOL process; right: thinned CMOS chip on a carrier chip with exposed Cu nails.
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3-D stacking is performed as a modified die-to-wafer bonding process, using Cu-to-Cu direct bonding. The stacking process consists of a fast die-to-wafer alignment and placement, followed by a collective wafer-level Cu-to-Cu bonding process, and can be repeated to obtain multi-die stacks (Figures 2 and 3). The key enabling technologies to realize the 3-D-stacked ICs are through-wafer via processing, wafer thinning, and Cu-to-Cu thermo-compression technologies.

Figure 3. Schematic representation of a 2- and 3-layer 3-D-SIC stack using Cu-to-Cu bonding.
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Strengths and Limitations

The 3-D-SIC Cu nail approach presents some important advantages. It puts minimal impact on CMOS wafer design and processing because of the small exclusion area on the FEOL, the absence of impact on the BEOL wiring, and the small number of necessary additional process steps. It has a highly parallel processing route: wafers are prepared for 3-D stacking and only KGD are stacked involving a minimum number of processing steps, achieving high 3-D-module yields and low-cost processing. The result is the possibility of realizing high-density 3-D interconnects, as the Cu nail size is only a few micrometers in diameter. Densities up to and exceeding 0.4 mm2 are feasible. The technique enables a wide range of applications, including 3-D-SoC types of applications.

The development of a mechanically and electrically reliable Cu-to-Cu bonding process is a challenge (Figure 4). This includes the choice of the dielectric bonding layer, the determination of an optimal bond layer thickness, avoiding Cu oxidation during handling and bonding, and an optimization of the bond strength. Initial thermo-compression Cu-to-Cu bonding experiments demonstrated the feasibility of this process step.

Figure 4. Initial Cu-to-Cu bonding experiment.
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Another challenge is related to the handling of very thin Si (10 µm). The impact on the device performance of using this very thin Si is still unknown. One possible drawback of this 3-D-SIC concept is the need for routing 3-D contacts through intermediate dies in the stack. This implies that the die, or at least the 3-D contact, must be arranged in a “wedding-cake” fashion. Combining this technology with ultra-thin-chip-stacking (UTCS) technology might enable other configurations. With UTCS, thin dies are stacked on active device wafers and are interconnected with the host wafer using a multi-layer thin-film technology, which allows for stacking dies with varying dimensions.


Evolution of microelectronic technology and electronic systems will demand 3-D interconnect technologies. Developed technologies can be classified according to the underlying manufacturing infrastructure. The technology of choice depends on the required interconnect density. The highest wiring density can be obtained using 3-D-stacked ICs realizing 3-D Si-through connections during the IC foundry process, between the FEOL and BEOL. This concept puts minimal impact on CMOS processing, the high interconnect densities, and the parallel process flow. The 3-D-IC Cu-nail process flow will be elaborated as part of an industrial affiliation program** aiming to find solutions for interconnect technologies for the 45- and 32-nm node and below.

** IMEC’s Advanced Interconnect Technology Program

BART SWINNEN, program manager, wafer-level packaging 3D-SIC, and ERIC BEYNE, director, Advanced Packaging and Interconnect Center, may be contacted at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; +32 16 281 880; E-mail: [email protected], [email protected].


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