By Bob Haavind, Editorial Director
Several approaches to metal gate processing and integration with high-k dielectrics for the 45nm node and beyond were reported at the recent International Electron Devices Meeting (IEDM) in Washington, DC.
Most presentations focused on nickel silicide (NiSi) as the metal with one- or two-step processes to achieve fully silicided (FUSI) gates, and some showed how they could be combined with hafnium-based high-k gate dielectrics. Nickel was a natural choice because it is already fab-qualified, and it also allows adjusting work function (WF) values up or down (depending on dopants). Analytical work on why the WF tuning works, suggesting how processing might be optimized, was also discussed. This approach avoids the complexity of using different metals for p- and n-channel devices with very short gate lengths.
Metal gates appear necessary as transistor scaling continues. The small charge depletion layer in the traditional polysilicon gate adds to the effective thickness of the inversion layer over the p- or n-channel linking the source and drain. This was no problem with a thicker gate dielectric, but it does become a problem with gate insulators only four atoms deep. Depletion from the poly has climbed from 3% of the channel thickness in 1985 to about 50% in 2005. If metal is used for gates to eliminate the polysilicon depletion layer, it can enhance inversion charge density, but different WF metals will be needed in p- and n-channel FETs to get the WF at the band edge for high-performance devices (perhaps 4.0-4.2eV for n-channel, and 4.9-5.1eV for p-channel FETs). Processing is critical because the WF of integrated metal gates is dependent on deposition and annealing conditions.
Intel chose NiSi for metal gates because it is already in the process flow for 90nm and 65nm devices, so formation kinetics and processing steps are already known. It has a near mid-gap WF that can be modulated up or down by doping the poly-Si, and has a low formation temperature (<400 degrees C), according to P. Ranade, et al.
A damascene “gate last” approach allows separate siliciding of the source-drain before the gate is exposed, so that the Ni thickness can be independently controlled. The FUSI devices showed a 20% improvement in inversion charge density over control devices due to the suppression of gate depletion. Experiments showed that phosphorous doping slightly lowered the WF while boron increased it. There was a 20% increase in drive current over the best achieved without the metal gate, Intel reported, and there was minimal impact on gate leakage, channel transport, and reliability.
The authors believe that the WF shift is caused by dopants piling up at the gate junction with the oxide, but they declined to discuss specific results.
A cobalt silicide (CoSi2) barrier layer over active regions was added to NiSi FUSI gates in work reported by S. Yu, et al., Texas Instruments, to block nickel diffusion and prevent further silicidication of the silicon substrate. Two rapid thermal processing (RTP) steps are used, and no mobility degradation was found between the 35nm FUSI and poly-Si gate devices. They reported performance improvements of 15% for n-channel and 31% for p-channel devices.
A detailed study of WF engineering and scavenging for NiSi metal gates was presented by Y.H. Kim, et al., IBM. They suggested that high-concentration ion implantation can have a snowplow effect, with dopant diffusion and delamination. In studying many materials, they found that adding aluminum and platinum to the NiSi improved high-performance device characteristics when the metal gates interfaced with hafnium (Hf) compounds. The additives provided more stable diffusion compared to NiSi, perhaps by decreasing the number of Hf-Si bonds, while also allowing WF shifting. Experiments showed that NiAlSi and Ni-rich PtSi were the best candidates studied, but that too much aluminum may degrade mobility.
Another study of WF modulation at the Ni-FUSI/SiO(N) interface was reported by Yoshinori Tsuchiya, et al., Toshiba. Many factors influence the WF, such as crystal orientation and material bulk properties as well as the silicide phase and the pre-doped impurity species, even under similar processing. The Ni/Si ratio significantly effects the bulk value of the WF. By separating the different effects, the authors found that the dominant affect is the pile-up of impurities at the interface between the silicide and the oxide. An effective WF model was developed based on the experiments. They suggest that the model explains not only the direction of WF shift, but also the range, indicating that precise control of impurity location is critical.
A novel single-step silicidization was described by M. Muller, Philips, along with coauthors from STMicroelectronics and CEA-LETI, Grenoble. To perform the junction and total gate silicidization in one step, the heights are adjusted with the initial poly-Si gate 30-50nm higher, capped by a thick oxide hard mask and selective epitaxy on the source/drain regions to raise the final silicizidation front. A two-step thermal treatment is used, with the second step at a higher temperature so the NiSi reacts with the remaining Si at the bottom of the gate. They called their devices “totally silicided” (TOSI), although the effect is similar to the FUSI work reported elsewhere.
These were only some of the interesting processing variations proposed for obtaining fully silicided gates with different WF for n- and p-channel NiSi devices. However, there may be much more exploration of this frontier going on in semiconductor laboratories all over the globe. At an evening panel on scaling challenges organized by Applied Materials, one reporter lamented that a lot of the most interesting work on metal gates and their integration with high-k dielectrics may not be openly discussed by researchers – and if so, the whole industry will have to struggle harder to solve the myriad problems remaining to get this technology into commercial production over the next few years. — B.H.