February 16, 2006 – Researchers at the U. of Wisconsin-Madison and French wafer supplier Soitec have determined that if specially cleaned, ultrathin layers of silicon actually do facilitate current flow — indicating that conductivity at the nanoscale is independent of dopants normally controlling silicon’s electrical properties.
The scientists used 0.5mm silicon-on-insulator substrates insulated by silicon oxide and another 10nm “nanomembrane” of silicon. Normal methods to remove oxidation from the top layer require temperatures of >1200 degrees C, which warps the membrane. But slowly depositing additional silicon or germanium layers using an ultrahigh vacuum (each one atom thick) at 700 degrees C, grad student Pengpeng Zhang found that the top oxide can be removed without causing damage to the nanomembrane — and what’s more, it also became a conductor. The scientists analyzed the resistance of silicon layers 15-200nm thick, and compared silicon’s resistance when sandwiched between two oxide layers vs. the newly vacuum-cleaned oxide layer. Modeling resistance as a function of layer thickness in both situations showed that the silicon properties became irrelevant in layers with <100nm thickness, and even with relatively thick layers of 200nm the vacuum-cleaned surface was >10x more conductive than sandwiched silicon. As layer thickness shrunk, the difference grew to six orders of magnitude.
The researchers postulate that the cleaning process creates extra electronic states on the silicon surface, which are filled by some of the electrons, which create vacated holes in the bulk silicon to be filled with other electrons, producing additional holes, and so on — leading to a current flow.
“It’s an interesting interplay,” stated UW-Madison physicist Mark Eriksson. “You clean the surface so you can image it. But then the surface ends up enabling conductivity in the entire silicon layer.”
The findings suggest that surface preparation is critically important when creating nanoscale devices. “It turns out that silicon conducts much worse than that if the surface is poorly prepared and much better than that if the surface is well prepared,” stated prof. Paul Evans, from UW-Madison’s College of Engineering. But it also means that many current methods and instruments used in the semiconductor industry requiring conductive samples, such as scanning tunneling microscopy, can also be applied to the nanoscale as well.