SEMATECH 3D project seeks interconnect answers

February 9, 2006 – SEMATECH has launched a new project to explore the feasibility of three-dimensional (3D) interconnect technology for the semiconductor industry. Work will initially focus on developing a cost model for 3D migration and a list of infrastructure needs for SEMATECH member companies, as well as building consensus on 3D technology standards. Future activities will involve proving feasibility of the technology for materials, unit processes, integration, and reliability.

The industry has pursued copper and low-k interconnect materials, which are now moving into real products, but decreasing k effective by changing dielectrics and assist layers presents the challenge of continuously developing and requalifying new metals, explained Sitaram Arkalgud, director of SEMATECH’s interconnect division. “The ITRS shows that low-k technology alone will not be sufficient to meet the needs of microdevices in 2010. Of the available options, 3D may offer the least disruptive path to the next interconnect paradigm.” He added that the new 3D interconnect project will augment SEMATECH’s low-k development program emphasizing chemical vapor deposition (CVD) films.

The program will focus on wafer-on-wafer and die-on-wafer structures, seeking answers for both high-performance and low-cost products, Arkalgud stated. A working group of about 20 SEMATECH member companies has been formed to assess key challenges of 3D interconnect and available options, and will develop a 3D roadmap with the ultimate goal of transferring the process to the ITRS.

3D interconnect involves the physical and electrical bonding of semiconductor wafers and dies, using deep through-silicon vias, to produce multilevel microchips with advanced processing capabilities. At volume production levels, it promises more cost-effective integrated chips that are easier to engineer.


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