ST touts 50% throughput boost in 4Gbit NAND

February 6, 2006 – STMicroelectronics and Hynix Semiconductor say they have developed a 4Gbit NAND flash memory device with throughput of 36MB/sec, roughly 50% better than available technologies. The device, unveiled at this week’s International Solid State Circuits Conference (ISSCC) in San Francisco, CA, includes an embedded error-correction processor to detect and correct up to 5 errors/page.

Multilevel cell NAND flash memories offer density and cost benefits vs. single-bit cell NAND flash, but also reduced data retention and memory cycling performance. This typically requires complex error correction code (ECC) circuits and an algorithm executed by the system processor which is not optimized for such instructions, resulting in a throughput penalty that is typically several MB/sec.

The new ST device, developed at ST’s nonvolatile memory facility in Agrate, Italy, employs an ECC processor embedded within the flash memory implementing the Bose-Chaudhuri-Hocquenghem (BCH) error correction technique, used in WLAN and other applications requiring detection and correction of multiple data transmission errors. The embedded ECC processor’s architecture optimizes ECC computations for byte-oriented, serial readout memory applications (e.g. MP3 players and USB keys).

The error correction circuitry is also partitioned to minimize time penalties when errors are detected — one of two separate error location blocks corrects 2-5 errors with a 250µm time overhead, and the other corrects the much more likely single error in only 34µm. The area occupied by the ECC circuitry is only 1.3mm<+2>, less than 1% of total chip area, with average current less than 1mA.

“This innovative breakthrough will fast become standard in ST’s two-bit/cell NAND flash roadmap,” said Carla Golla, GM of ST’s NAND flash memory division, adding that ST hopes to make the approach an industry standard feature in such devices. “This method realizes the cost advantages of multilevel cell technology, but without sacrificing system read throughput and reliability.”


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