The IC Package

Missing Link between Nanometer Silicon and Multi-gigabit PCB systems


As nanometer-scale ICs become commonplace andprinted circuit board (PCB) system data rates achieve multi-gigabit levels, it is increasingly important for designers to consider the entire system interconnect – from IC to package to board to package. From this vantage point, IC package design takes on new importance. It becomes the critical link in the signal and power paths where money and time are gained or lost.

Courtesy of Amkor Techonlogies, Inc.
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In the face of this pressure, high-speed IC package designers must ensure both signal and power integrity by making certain IC package structures are properly modeled, extracted, and simulated with the rest of the circuit on both signal and power delivery paths. Fortunately, integrated modeling and analysis techniques and tools are available to describe a complicated package structure with true 3-D representations, and simulate those representations in the context of system interconnect. These tools help designers consider the package effect from designs and make decisions based on actual conditions, thus reducing design iterations, cycles, and development time.

3-D Modeling

As modeling is an integral part of the design and analysis of IC packages, it is important to look at the options. For the past two decades, 2-D field solvers have been used successfully for modeling traces on PCBs. However, increasing package complexity and density has resulted in signal traces with more vias, segments, and discontinuities. Complex packages place traces on many layers. Package-interconnect elements, such as nonorthogonal traces, vias, wire bonds, and solder balls must be modeled. As 2-D field solvers cannot address 3-D behaviors, 3-D solutions have to be used. There are two types of complementary 3-D field solvers – full-wave and quasi-static – that are useful in representing package behavior, depending on the application. Both can be used in conjunction with 2-D solvers.

Figure 1. Electrical field distribution on a long differential pair.
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As illustrated in Figure 1, signals propagate in a simple transverse electromagnetic (TEM) mode on long transmission lines. For these designs, traditional 2-D field solvers are accurate enough and much faster than 3-D field solvers. However, Figure 2 shows how signal propagation modes in packages require a 3-D field solver.

Figure 2. Electrical field distribution of a package model.
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Quasi-static and Full-wave Field Solvers

Quasi-static field solvers are used when signals traveling on conductive paths have lower speeds – usually data rates below 5 Gbps. Quasi-static solvers produce field solutions by ignoring the displacement current. With such simplification, electrical fields remain static outside conductors, but magnetic fields retain frequency dependency inside conductors so that the skin effect can be accounted for properly. Capacitance (C) and conductance (G) of a structure are determined by electrical fields only; resistance (R) and inductance (L) are determined only by magnetic fields. In other words, by ignoring the displacement current, magnetic and electrical fields are decoupled in the quasi-static theory, and can be solved independently. Because of the decoupling between electrical and magnetic fields, a quasi-static field solver is quicker and can solve much bigger problems than a full-wave solver. Many modern quasi-static solvers can perform whole-package RLGC extraction of a complicated package design in a few hours.

Most designers wonder about the highest frequency at which the quasi-static assumption is still valid. While it is difficult to provide a universal upper limit to the applicability of quasi-static solvers, in high-speed package designs, 3 to 4 GHz is an acceptable value.

Full-wave field solvers are used in cases where strong electromagnetic coupling, resonance, and radiation require accurate solutions of Maxwell equations. A full-wave field solver is capable of solving Maxwell equations at any given frequency. It solves electrical and magnetic fields together so that the interaction between electrical and magnetic fields is handled properly. As a result, this type of solver can take into account displacement currents, electromagnetic radiation, and field coupling. Because there are limits in computer capacities, full-wave field solvers are best applied to obtain solutions of small geometries; for example, coupled critical signal traces carrying 12.5-Gbps signals.

In practice, designers will use 3-D field solvers in addition to 2-D solvers. While the choice of field solvers is application-dependent, any field solver must be integrated into a design system that enables engineers to explore, design, implement, and verify interconnect topologies and electrical constraints through simulation. Such an integrated environment can eliminate time wasted in translations and re-entering of design data, in addition to ensuring product performance.

Integrating Packaging Effects in High-Speed Design

Today’s high-speed digital systems are characterized by high current capacity, high data rates, and low voltage, forcing design focus on power delivery. The challenge of providing sufficient and stable power to active devices through PCBs and packages elevates power delivery design to the system level. To solve the problem, the IC, package, and board must be considered.

To illustrate how designers can use 3-D package representations and efficiently simulate those representations within a cross-domain environment, an example demonstrates addressing signal delays by modeling package interconnects with a quasi-static 3-D field solver, and by simulating the entire signal paths from output buffers to input buffers. This differs from the typical current flow/methodology where the power supply to the IC core is assumed ideal, or at best, attenuated by a lumped, fixed-impedance, approximated load meant to represent the IC package and the PCB.

Figure 3. VSIC model of a buffer-to-buffer interconnect pathway.
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Figure 3 shows the die-to-die signal path and highlights the importance of working in an integrated design and analysis environment that allows for cross-domain communication. It is a virtual or abstract system interconnect model (VSIC), which enables complete modeling and analysis of the interconnect across silicon, package, and PCB. The redistribution layer (RDL) model is drawn from the IC database, the package parasitics from the IC package tool, and the board trace models from the PCB layout tool.

Figure 4. An integrated environment provides a complete solution for system-level timing analysis.
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Figure 4 provides a look at the simulation flow for the same circuit within the design and analysis environment. Following the simulation flow, a net on the design can be modeled in three pieces: the RDL equivalent model, the 3-D package model, and the 2-D board trace model. By simulating the extracted circuit, signal distortion and delay between output buffer and input buffer can be measured.

To ensure power integrity, two fundamental design requirements must be met. Sufficient supply voltage and current must be delivered from the battery to ICs through PCBs and packages, and the supply must be kept clean and stable during the operating range of the device.

Sufficient power supply to the IC core circuitry demands a low impedance path for the entire power delivery network, while the stability of supply voltages requires the power delivery network to have the desired level of noise immunity induced by simultaneous switching of high-speed signals during device/system operation. If a low-impedance path for a power delivery network can be maintained, then a stable power supply should be achieved easily. Easier said than done? Not if this often-overlooked missing link is taken into consideration – the successful provision and maintenance of a low-impedance path for the power supply at the frequency range of interest.

To create an ideal low-impedance path, an effective plane configuration on the PCB and corresponding power and ground net structures on the IC package is used. If the target low impedance cannot be achieved, a decoupling strategy must be used. Although the design of a low-impedance path can be achieved using frequency-domain simulation, the final power supply network should be verified in the time domain to see how much power has been lost through the PCB and package, and if the power supply variation (voltage ripple) is controlled within a certain budget when noise is injected into the power supply network.

Both the design and verification phases can be achieved by modeling each element of the power delivery path and performing an overall simulation of the entire path. Because of the geometric complexity of the power and ground nets in an IC package, and the overwhelming circuit size of the power grid in an IC, one simulation tool can not be expected to simulate the entire power and ground paths. Therefore, it is essential to use integrated flow of simulation tools that support either IC, package, or board-level simulation.

Key to making this methodology viable is the adoption of an integrated co-design methodology between the IC core and package design. By using a co-design process, the actual IC die-to-package interfaces (IC-core, verilog port names and IC-package, die-footprint bump names) can be mapped and used for building a complete power and ground network from voltage source to IC die; including the intermediate IC package model, which is modeled as a true 3-D quasi-static model. This power and ground supply network 3-D model of the IC package (Figure 5) is connected to the power grid on the IC core, enabling dynamic IR-drop simulation.

Figure 5. 3-D model of the power and ground networks created by a quasi-static field solver.
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In real design cases, worst-case IR-drop can be 20% higher when package effects are included in the IR-drop simulation than when they’re not. Therefore, by using a methodology that allows for IC package co-design and analysis, more accurate results are achievable, and a right-first-time tapeout for both the IC and the IC package is possible.


High-speed system design must consider IC package effects to alleviate SI and power delivery problems of final assembled devices. Both full-wave and quasi-static field solvers are needed to represent package behavior. Despite common belief, 2- and 3-D field solvers are complementary to each other in targeting different applications. A simulation environment with integrated field solvers is essential in providing complete signal integrity and power delivery solutions for high-speed IC/package and PCB designs.

AN-YU KUO, Ph.D., CTO, may be contacted at Optimal Corp., 6980 Santa Teresa Blvd., Suite 100, San Jose, CA 95119-1346; 408/363-6300; E-mail: [email protected]. ZHEN MU, Ph.D., senior technologist, may be contact at Cadence Design Systems Inc., 2655 Seely Ave., San Jose, CA 95134; 408/943-1234; E-mail: [email protected].


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