TI, MIT tout lowest-voltage 65nm SRAM

February 9, 2006 – Researchers from TI and MIT, funded by DARPA, say they have developed have developed what they claim is the industry’s lowest-voltage 65nm-based SRAM.

The 256Kbit static random-access memory (SRAM) device, utilizing TI’s 65nm CMOS process technology and SmartReflex power management technologies, achieves 0.4V sub-threshold, a 2.25x reduction in leakage power compared with a 6T device at 0.6V. The SRAM incorporates 10 transistors/bitcell to enable operation down to 400mV.

The joint program aims to reduce voltages to the sub-threshold level to save energy and enable simultaneous ULP and high performance. The participants also aim to develop memory modules and logic and switching mode power supplies (SMPS).

“Ultralow power [ULP] operation is critical in a variety of emerging commercial and military applications,” said MIT prof. Anantha Chandrakasan. “Scaling to such low supply voltages is critical to minimum energy processing and enables Ultra-Dynamic Voltage Scaling (U-DVS). The goal of this ULP technology is to reduce energy by an order of magnitude with minimal loss in system performance.”


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