February 28, 2006 – Cadence Design Systems Inc., Magma Design Automation Inc., and Synopsys Inc. have all announced new versions of their design flows for the 90nm common process platform developed by IBM, Chartered, and partners.

Cadence says its flow, based on the Encounter digital IC design platform, enables timing-aware leakage power and dynamic power optimization, using power techniques such as multi-supply voltages, multiple-Vt optimization, and clock gating to improve timing closure and reduce device area, while lowering power consumption.

Cadence claims its flow is “yield-aware,” with yield analysis and optimization capabilities embedded in critical implementation stages such as physical synthesis and routing. Prototyping capabilities let designers choose full-chip floorplanning strategies with visibility of yield considerations before committing to a physical architecture for the chip, and optimize double-via insertion, wire spacing, and other factors concurrently during routing, instead of a separate post-processing step.

Magma’s flow incorporates several products from its Blast lineup to address power management issues including dynamic power, leakage power, and power distribution. The low-power reference flow, part of a broader design enablement kit for the IBM-Chartered platform including a test design, RTL-to-GDSII script, and methodology guide, has been qualified by IBM and Chartered using real-world designs and libraries, the company said.

Synospys’ reference design flow, validated using ARM Metro physical IP, incorporates Synopsys’ Galaxy design platform implementation products, including IC Compiler place-and-route system. The company says the flow supports both flat and hierarchical design techniques, and is consistent with that of its recently released Pilot Design Environment.