By Hank Hogan
For semiconductor processing, being small is big-especially if you’re the first to reach a process node. That’s why the late-January announcement by Intel (Santa Clara, CA) about working memory chips produced in a 45-nanometer process-the next step below current state-of-the-art 65nm manufacturing-attracted attention.
Intel won’t divulge contamination-control details; however, there are educated guesses about the impact of this advance. “Generally, semiconductor industry experts use a 50 percent defect-size rule of thumb,” says Steve Silverman, president of Bartlett Bay Consulting, LLC, a company with contamination-control expertise in the semiconductor and pharmaceutical industries.
This guideline means that a 45nm process will need to account for particles that are about 20nm in size. That requirement ripples through all aspects of contamination control. The direct impact on cleanroom particle levels may be small since wafers will be exposed to mini-environments and not the cleanroom as a whole. For mini-environments, though, there’s a challenge. Present technology, says Silverman, can ensure ISO Class 1 with a particle size measurement standard that’s typically 100nm. Moving down by a factor of five in particle size could boost mini-environment costs substantially.
There’s also a problem with simply measuring particles of that size. Standard laser particle counters won’t work, and so an alternative approach, called a condensation nucleus counter (CNC), may have to be used. John Mitchell, vice president of marketing at particle counter maker Particle Measuring Systems, Inc. (PMS; Boulder, CO), points out that CNC technology isn’t ready yet to detect 20nm particles. The reasons, he says, have to do with the power of the lasers employed and other aspects of the detection scheme. Mitchell expects the measurement challenge to be met by CNCs or some other method, but the cost may be too high to be commercially successful.
A less-expensive approach would be to measure larger particles and establish a baseline. Mitchell notes that if the distribution of larger particles is unchanged, it’s likely that the distribution of smaller ones is unchanged, as well. However, he notes that this technique can have its own difficulties, which, ironically, can arise because an environment is too clean. “The problem comes when there are not enough large particles to provide meaningful data,” he says. “If all I see are zeros, it is impossible to extrapolate to smaller sized particles.”
This picture shows a close-up view of Intel’s 300mm wafer with 45nm shuttle test chips. Photo courtesy of Intel.
Michael O’Halloran, director of technology at the cleanroom construction firm CH2M HILL IDC (Portland, OR), notes as the particles of interest become smaller, they become indistinguishable from molecules. As the feature size drops to 45nm and below, airborne molecular contaminants (AMCs) are likely to be a major cleanroom contamination-control concern. In the past, AMCs have been a problem for certain devices or particular process steps, but not for an entire manufacturing line.
O’Halloran sees increasing attention being paid to make-up air handlers, the positioning of external intakes, and the airflow outside the cleanroom. That’s because airborne pollu-tants outside a cleanroom could end up inside as a result of air handling and make-up air. Removing the molecular burden from the incoming air and avoiding the entraining of airborne contaminants will help control AMCs and extend the life of the chemical filters intended for AMC control inside the cleanroom.
The problem of contaminated outside air will be most severe for facilities operating in areas with a high constant level of ambient pollution. However, it’s important to note that in this case, the average may not be that significant. Instead, it may be the worst case that’s of most concern and the most difficult to predict. “If you’re next to a freeway and there is a traffic jam and the wind’s blowing towards you from the freeway, you may have a problem,” says O’Halloran.