Alliance trio lines up DFM support for 65nm process

March 30, 2006 – Chartered Semiconductor Manufacturing Ltd., IBM Corp., and Samsung Electronics Co. Ltd. have announced availability of design-for-manufacturing (DFM) technology, models, design kits, and data files for their common 65nm process technology platform.

The capabilities and support from Cadence Design Systems Inc., Clear Shape Technologies, Magma Design Automation, Mentor Graphics, Ponte Solutions, and Synopsys Inc. help facilitate faster ramp to volume and better yields. A set of 65nm DFM layout guidelines, developed through shared learning by the alliance partners, is also available.

The collaborate DFM effort, first outlined in September 2005, identifying several key areas of focus involving design closure challenges including timing, area, power, signal integrity, and manufacturability. DFM capabilities offered through the rules- and model-based design kits include:

– DFM checking decks for rules compliance checking (from Mentor Graphics);
– critical area analysis to identify potential yield sensitivity hotspots (Ponte Solutions);
– lithography simulation across process windows to find hotspots at standard cell, IP and full-chip level (Mentor Graphics);
– CMP modeling of full-chip thickness variation (Cadence);
– full-chip-level shape simulation and design-manufacturability-check (Clear Shape Technologies); and
– DFM support in place-and-route reference flows (Cadence, Magma, and Synopsys).

Tool support for simultaneous yield and leakage optimization is being provided by an unidentified DFM company.


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