Breaking the Flip Chip Pitch Barrier

Keeping up with electrical and mechanical requirements

By Elwyn Wakefield, Micro-design Consultants

Component designers wishing to use wafer-level packaging (WLP) are frustrated with the inability of current-volume flip chip technologies to accommodate 150-µm pitch that has been used in high-volume wire bonding for over 30 years. Established techniques for wafer bumping fall into two main categories: those that are pitch-limited by trying to accommodate the industry-standard, surface mount solder reflow process, and those attempting to accommodate much finer pitches – as used in wire bonding – but need specialized, expensive, chip-bonding equipment.

The challenge for both is the low coefficient of thermal expansion (CTE) of the silicon chip. The CTE of silicon is approximately 15 ppm/°C lower than standard, organic laminates. If both silicon and board are heated by 200°C, the board footprint ends up being 0.3% larger than the chip footprint. Adjusting the board artwork doesn’t help, since the “zero-stress-point” of the structure will be fixed at, or just below, the melting point of the solder, or epoxy Tg; after which further cooling will result in increasing levels of shear stress being applied to the joints.

Over the years, various means of alleviating these stresses have been tried. The C4 process used a high-lead solder, low-CTE ceramic boards, and epoxy underfill. Peripheral bond pads were moved nearer to the center, where the absolute displacement was less, and arrayed to maximize the pitch, allowing larger bumps to be used. This increases the gap between chip and board, reducing the shear force at the interfaces, and allowing space for underfilling. Using a combination of these techniques, a 15-mm chip could successfully be attached, with a 250-µm full ball array that will survive thousands of thermal cycles.

Improvements in surface mount technology have enabled BGA pitches to be reduced to 0.5 mm and less, making it possible to directly solder some of the chips to the motherboard. Many lower pin-count devices are already being supplied as WLPs. However, on larger chips, without the assistance and protection provided by the interposers and encapsulation, stress management is a major issue, and limits the maximum die size that can be directly mounted onto laminate using standard reflow techniques. For some larger pin counts, a redistribution layer converts the peripheral pitches into an array of balls, providing some stress relief. Because the process of converting a chip into a surface-mountable component can be performed directly onto wafers prior to dicing, the potential exists for eliminating the need for conventional packaging if these WLPs can be reliable at the system level.

Stud-bump bonding approaches the problem from the opposite direction. Using the industry-standard, high-volume, gold thermosonic wire bonding equipment, a ball is bonded directly onto aluminium pads. The second “fishtail” bond is skipped, and the wire broken just above the ball resulting in a flattened bump with a short spike on top. In some applications, these bumps are “coined” by applying a downward force through a co-planar surface. Otherwise, the spike is left intact, increasing the separation between the chip and board, and providing some degree of co-planarity compensation. Soldering these parts can be problematic, and lower-temperature, adhesive-based processes tend to be used to overcome the increased residual stresses, resulting from lower chip-to-board separation. However, board cost and placement accuracy are still major issues.

Until there is a major advance in both PCB manufacture and soldering technology, some form of interposer will be required for most semiconductors, and the real challenge is to minimize the cost of conversion. Reducing the package size down to that of the silicon can result in savings of materials cost, but packaging all of the chips on the wafer simultaneously is still the best way to reduce assembly cost.

Cheating the Roadmap

Unfortunately, many silicon designers are way ahead of available capability. In some cases, designers have designed flip chip components and produced wafers using design rules supplied by the fab or bumping contractor, only to discover that finished chips cannot be assembled into the system, or even packaged for design verification.

The following case histories demonstrate how a recent enhancement to the stud-bump process, known as “micro-post,” 1, 2 has been used to overcome some major hiccups. These micro-posts differ from stud bumps because the majority of the ball winds up inside the bore of the capillary, providing a smaller attachment area and more precise shape control. Deliberate sculpting of the cone and bore of the capillary can optimize post profiles, so they can be exactly tuned to both the mechanical and electrical requirements of the system. A typical post profile consists of a truncated cone, on top of which is a short column, followed by a spike formed during wire break (Figure 1).

Figure 1. Typical profile. Courtesy of First-level Inc.
Click here to enlarge image


PIN Diode on Ceramic

Several gallium arsenide (GaAs) PIN diodes needed to be attached to standard alumina ceramic for a military application. The chips are small and have no major stress issues, as the CTE of GaAs is relatively low and very close to alumina. For high reliability at extreme temperatures, the production process was intended to be either gold or gold/tin bumps.

Availability was the issue. Initially, only 10 assemblies were required, with a total of 80 PIN diodes. Solder-bumped chips were available, but only in 60Sn/40Pb, and the cost of buying a whole wafer and sub-contract bumping was prohibitive. It was not possible to mechanically clamp individual die well enough to use standard stud bumps direct onto the chip, as GaAs is very brittle, and the bond pads were only 30-µm diameter.

The post profile started at 60-µm diameter to match the pad size on the ceramic substrate, on top of which was a 40-µm shaft, finishing in a 25-µm spike. Posts were attached to the substrate using a standard* gold thermosonic bonder, and overall time for bonding and extruding each post was <50 mS. The GaAs chips were subsequently thermo-compression bonded at 350°C and 0.5 N, with a 250°C substrate temperature. The time for bonding each chip was <1 s, and as all mating surfaces were either gold or gold-plated, an inert atmosphere was not required.

Flip Chip on Chip

In a combined project between two universities,** GaAs sensor arrays needed to be flipped onto a standard silicon ASIC. The final application would use solder bumps, but for prototype assembly, only singulated, un-bumped chips were available; and prototypes needed to be assembled quickly to secure further funding.

Posts were bonded to 100-µm aluminium pads and arrayed on a 250-µm pitch in the middle of the ASIC chip. As the CTE of GaAs is only 3 ppm/°C higher than silicon, stress was not an issue. Both surfaces to be bonded were optically co-planar, so relatively short, stiff posts were used. Next, sensor chips were attached using a flip chip bonder. The ASIC chips with mounted sensors were shipped back and attached to ceramic carriers using conductive adhesive. Standard aluminium wire bonds connected the peripheral pads on the ASIC to their respective connections on the ceramic carrier. 32 × 32 arrays have subsequently been produced on 100-µm pitch (Figure 2).

Figure 2. 1K micro-post array. Courtesy of Mintech Semiconductors Ltd.
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Flip Chip on Laminate

Although chips with posts have been assembled using 60Sn/40Pb, 95Sn/5Ag, and 80Au/Sn alloys, the most widespread use of post technology has been in conjunction with conductive adhesives. Initially, it was thought that coined stud bumps would work best for this application. Whole wafers were produced before it was realized that laminates were not co-planar. As a result, either some bumps failed to make contact with the adhesive, creating open circuits; or paste squeezed out between adjacent bumps, causing short circuits. A taller, slimmer post profile proved far more suitable; able to compress in response to board undulations, and having larger spaces between adjacent connections.

Devices have been shipped with post heights ranging from 60 to 450 µm. Various laminates and flexibles have been assembled using conductive adhesives applied by pneumatic dispensing, screen printing, and “dip and stick;” and prototypes have been produced using ACA, NCA, and NCF.

Exploding Bumping Model Myths

The assumption is that solder bumping must be cheaper than “serial processes,” such as wire bonding. However, unless volumes are high, this is not the case. Applying bumps and posts at wafer-level is extremely cost-effective. They can be bonded 3× faster than traditional wires, and use less than one-tenth the amount of material. There are usually no tooling costs, and first articles can be available within minutes. Compared with some solder-bumping process, it may take 100 wafers, or more, to break even. With additional costs of under-bump metalization (UBM) and redistribution, even 1K wafers may not be enough to recover the costs.

Figure 3. Micro-posts on 8-in. wafer. Courtesy of Clearspeed Ltd.
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Solder bumps don’t always give better electrical performance than wire bonds if a redistribution layer is used. In some FC-BGA parts, signals may be routed at 20-µm line and space through several rows of solder bumps before emerging from the redistribution plane near the center of the chip, only to be subjected to a similar path back out to the edge of the BGA, and continue on to the next component in the chain. In many cases, the path length within the FC-BGA can be a few centimeters or more. When using flip chip in system-in-package (SiP), maintaining a one-to-one relationship between the bond pads on processors and memory device can be essential, and rearranging signals into a bump array on a larger pitch can lead to distortion, timing errors, and crosstalk.

Latest Developments

Work has begun on micro-post WLPs. Having applied the posts to the wafers, they are coated with plastic, leaving the tips exposed. The wafers are mounted and sawn. Non-functional parts, as indicated on the wafer map, are removed prior to shipping, and the chips transferred to carrier tape or shipped still attached to the film frame.

In one application, a thermo-plastic film is applied after the posts are attached, so the parts can be directly placed on pre-tinned boards using a heated pick-up on a high-speed chipshooter. The thermoplastic acts both as an adhesive and an underfill, and prevents oxidation of the tinned surface during reflow. The board does not need to be pre-heated, so the CTE mismatch is reduced to only 2 ppm/°C.

In another development exercise, the whole wafer was coated in epoxy, and subsequently etched back to form cavities around the tips of the posts. Prior to dicing, they were filled with solder, thereby creating miniature surface-mountable WLP-BGAs (Figure 4).

Figure 4. Post in epoxy. Courtesy of Tessera Inc.
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Using equipment and processes left over from the era of wire bonding, advanced bumping techniques are successful in areas where other technologies failed. With equipment and materials specifically designed to exploit the full benefits of shaped bumps, it is possible to keep up with both the electrical and mechanical requirements imposed by reducing chip sizes.

*Kulicke & Soffa 1480
**Cambridge and Oxford Universities


  1. “An Innovative Approach to Low-cost, High-performance, Lead-free DCA” Elwyn Wakefield; IMAPS – Flip Chip Technologies Conference, Austin, Texas, June 2005.
  2. “Micro-post Assembly Process” Nabil Homsy: IMAPS – 38th Annual Symposium on Microelectronics, Philadelphia, September 2005.

ELWYN WAKEFIELD, consultant, may be contacted at Micro-Design Consultants; +44/ 1354 691751; E-mail: [email protected].


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