Japan lays out 45-32nm R&D plans

March 30, 2006 – The Japanese government and domestic semiconductor manufacturers have finalized their plans to forge a new five-year, 90 billion yen (about US $770 million) plan to design and produce next-generation semiconductors using 45nm and 32nm process technologies. The proposal for the new program, named Asuka II, were tentatively unveiled last July.

Industry R&D consortium Semiconductor Leading Edge Technologies Inc. (Selete) will invest about 50 billion yen ($427 million) in the new project, with another 20 billion yen ($171 million) each from the government and from the Semiconductor Technology Academic Research Center (STARC). The Japan Electronics and Information Technology Industries Association (JEITA) is targeting readiness of 45nm manufacturing technology in fiscal 2007, followed by a 32nm process by fiscal 2010. Domestic chipmakers already have been working on their own to develop 65nm-55nm technologies.

Selete currently encompasses 11 domestic chipmakers, but in two years four leading domestic chipmakers — Toshiba, Renesas, NEC, and Fujitsu — will take majority ownership of the project taking a majority of the stake, and thus most of the fruits of the R&D work, noted the Nihon Keizai Shimbun.

The previous Asuka program, focused on 90nm technology development, is winding down to completion in the current fiscal year ending this month.


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