March 13, 2006 – Four schools in California have joined to establish the Western Institute for Nanoelectronics in an effort to explore spintronics as a possible alternative to silicon CMOS for semiconductor devices beyond the 65nm node. The Institute will be housed at UCLA, with scientific and technical responsibilities distributed across all four campuses of participants Stanford, UCLA, UC-Santa Barbara, and UC-Berkeley.
Spintronics involves utilizing the spin of an electron to carry information — whereas conventional charge-based devices move the charges around, spintronics aims to corral that spin and create a smooth reactive chain of motion.
Today’s devices, based on CMOS standards, “can’t get much smaller and still function properly and effectively. That’s where spintronics comes in,” stated UCLA engineering prof. Kang Wang, director of the institute. Stanford prof. Philip Wong identified areas of research including physics and materials, as well as exploration of devices, circuits, and spin filters. Jim Plummer, dean of Stanford’s school of engineering, noted that a clear successor to silicon CMOS has yet to be identified (if it exists at all), but “we must search for it and this multiuniversity team is well positioned to do this.”
The Western Institute of Nanoelectronics is being established by $18.2 million in grants, to be distributed over a four-year period, including $2.4 million from six sponsors: Intel, IBM, TI, AMD, Freescale, and Micron. Intel also is granting an extra $2 million and $10 million for equipment. Infrastructure and personnel support from the participating universities is projected to top $200 million.