Advanced Interconnect Comes of Age

Single-Cell Process Streamlines Bumping


The shortest distance between two points is still a straight line. In interconnect, until recently, this rule refers to a wire approaching tenth the size of a human hair. Now, as chip design advances to <90 nm gate widths, and interconnect technologies scramble to respond, the shortest distance between two points may simply be a shorter line.

Wire Bonding: Hitting a Wall?

Wire bonding still owns more than 90% of the IC market. It ably creates pathways to propagate signal from the semiconductor input, condition the signal, and convey it through an output to the next stage. To date, wire bonding has kept pace with IC demands, but the challenge is building. Since 1992, the average number of interconnects for a non-discrete IC has increased from 40 to more than 1000. That means the time required to wire-bond a high-density chip has lengthened dramatically, and so has the cost.

In 1992, most portable electronics didn’t have the operational frequencies and power of today’s devices, such as DVD, telecom, wireless and Internet access, gaming, graphics, 2-way communications, digital cameras, and GPS systems. These smaller, high-performance electronic products must address RF switching, RF power, streaming data/video, high-speed digital, extensive information “packets,” and electronic synergy between host and device.

Wire bonding will remain the primary interconnect for many years to come. However, the manufacturing requirements of high I/O, high-performance devices pose a challenge for wire bonders. The minimum diameter of a wire that can be bonded is 12.5 µm, and bond pad pitches of 25 µm are only being achieved in laboratories. Reaching the 20-µm pad pitch predicted by the ITRS will require a 10-µm wire. At that diameter, the slightest disturbance in the ambient air – even a breath exhaled by a technician – can move the wire off the pad during bonding. Furthermore, it is unknown how many electrons can be sent through a 10-µm wire. Thus, the lower limits, beyond which wire bonding cannot meet the requirement, have been identified.

Expanding Interconnect Options

To answer this challenge, new interconnect modalities such as nodes, bumps, buttons, spheres, and pillars have surfaced. New processes like electroplate, electroless, litho/screen, and in-situ have been developed, and involve new materials such as aluminum, gold, tungsten, titanium, nickel, copper, tin, lead, and silver. Conventional area-array (BGA and CSP) and wafer-level packages possess intrinsic properties that solve some RF or high-speed digital problems, while introducing others. Concerns such as cross-talk, noise, propagation delays, impedance, parasitic electricals, and thermal issues are magnified by portable design and the tight proximity of semiconductors.

Wire bonding and bumping have target applications with overlapping benefits and advantages. Bumped IC offers a suite of solutions to issues like thermal dissipation, electrical performance, form factor, weight, and speed, enabling miniaturization of OEM electronics. These are similar issues addressed by wire bond, but differ in how high-speed digital and RF operational characteristics alter the functional operation of electronics. When transfer rates exceed 2.0 Mbps or 500 MHz, material properties change, and have an unfavorable influence on the behavior of the IC or semiconductor.

Critical control and uniformity are becoming paramount in the integration of process, tools, and materials because of this growing phenomenon; and the lack of understanding this is the reason that bumping has not been readily adopted. After all, why replace a functioning IC process with its support systems and vendor bases with one that requires new and different equipment, material, and expertise?

Interconnect: Process, Tools, and Materials

To date, bumping has been a costly IC method because equipment manufacturers have overlooked the objective of producing an affordable solution, more than simply a tool. However, a flexible, cost-effective solution exists that is scalable to fit in any setting, from the R&D lab to high-volume manufacturing. This process is also adaptable to chip scale or wafer-level packages, micro-vias, posts, bumps, hybrid circuits, LCD screens, etc.

Manufacturing technicians, engineers, assembly and test sites, circuit designers, technical developers, and systems designers specified that this process must be electrolytic and support a multi-metal stacking capability. It needed to be scalable from low to dense I/O ICs and offer quick changeout for chemistry and material sets. The tool must also be lead-free-capable, have optimal chemical usage and low waste, and reduce the amount of handling, while providing controlled, uniform plating. From a cost perspective, industry experts required a low cost of acquisition and ownership, along with ease of use, to ensure a low-level training investment. A smaller footprint with double the plating capability of other systems was also necessary.

Analogous to what the PC did to the mainframe, the new process is centered on a tool that offers an alternative to the huge and extensive tools available. The concept is for the product – whether it be a wafer, tab or coupon, PCB, substrate, or LCD – to remain in the cell for all process steps in a fully integrated approach, unlike the typical serial process where the wafer is removed and presented to various tools for discrete process steps (Figure 1).

Figure 1. Current process using multiple serial cells.
Click here to enlarge image

This new, proprietary process tool performs all steps in one controlled chamber without having to remove the wafer and transport it to other process steps. The single cell concept responds to a myriad of issues facing IC designers, product designers, OEM electronics manufacturers, systems designers, wafer fabricators, IC packaging assemblers, and others who require a bump solution (Figure 2).

Figure 2. New process using a single cell.
Click here to enlarge image


Toward the Perfect Interconnect

How could a single tool and recipe perform bumping in one process step? Approaching the entire interconnect process as one process solution is the key to meeting the challenge of cost-effective, volume interconnect. The system maintains a secure manufacturing environment by managing the process and the chemistry, and brings attractive throughput rates to what has traditionally been a slow and costly process. Most important, recognizing the discrete but symbiotic relationship between the three prime domains of process, tools, and materials makes wafer bumping the advanced and affordable interconnect technology that the semiconductor industry requires.

STEVE ANDERSON, CEO, may be contacted at Surfect Technologies Inc., 12000-G Candelaria N.E., Albuquerque, NM 87112; 505/294-6354; E-mail: [email protected].


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