Breaking Down the Barriers for True Innovation


Senior executives at semiconductor companies worldwide have an innovation crisis on their hands. Hardware design teams, which include electrical and packaging engineers, are divided by an invisible barrier due to historical company organizational charts and the inability of their design software tools to work together that prevents them from building truly creative, innovative designs. But it really is the same old story: the hardware designer throws the design over the wall and forgets about it, assuming that the package is the packaging engineer’s problem. It lands on his or her desk and he or she is forced to figure out how to implement it.

For entrepreneurial companies – or even those with the desire to reclaim the competitive edge and recreate their innovative culture – this is unacceptable. With packaging playing an increasingly important role, a new approach to integrated circuit (IC) design that is package- and system-aware is the only way to reclaim a culture of innovation.

The question is: What will it take to break down the barriers for true innovation?

First of all, chip floorplanning and I/O placement can no longer be done in isolation. Instead, a comprehensive approach that allows a concurrent design methodology for chip and package is a must, with I/O planning part of the overall system design flow. Chip designers don’t need to become packaging experts, but packaging guidance should be built into their design tools. And they need to understand some packaging concepts that have been ignored. Early automated I/O planning can help ensure good I/O performance for signal and power integrity and physical implementation, helping to lower overall cost. An early I/O and package plan lets chip designers analyze the entire interconnect, from the chip’s I/O buffers to the PCB.

A typical 2,000-pad flip chip system-on-a-chip (SoC) has 6 to 12 layers with an intricate escape pattern of interconnects and vias. While package design rules are flexible, flexibility comes at a cost. The packaging engineer can decrease the interconnect pitch to fit more routes in congested areas, but the finer pitch reduces manufacturing yields, increases package cost, and can cause signal integrity problems as well. The packaging engineer has other options, including increasing the number of layers, but each additional layer increases the package cost.

Package design is a manual process because it involves many layout, cost, and performance judgments rather than fixed routing rules. As a result, skilled packaging engineers can minimize costs and performance problems and accommodate the I/O layout done by the chip designer. Chip designers rarely create I/O layouts with packaging in mind, which means finding a workable escape pattern is often a long and painful process. It’s not unusual for the design of a typical 6-layer package to take between 4 and 6 weeks.

A holistic approach to chip design that includes the impact of package parasitics on interconnect performance has become important. It guarantees that all elements are taken into consideration as part of the optimization process, and can accept various constraints from diverse design domains, including PCB, package, and IC. It also produces optimal placement of I/Os, associated logic, bumps, and routing on the top layer from I/Os to bumps. A capability to synthesize bump patterns will help achieve timing closure, identify signal integrity requirements, and escape in the given package substrate layers. Developing such a solution for full chip integration early in the design, with the ability to simultaneously visualize the chip in the package, ensures design convergence. With information from the chip designer on the package I/O assignments, a packaging engineer can create the initial package layout at the beginning of the silicon design flow. This updated design flow moves hardware design teams from traditional sequential design of chip and package to a concurrent design approach.

Chip designers have ignored packaging and endured longer time-to-market, higher costs, and compromised performance. With package-aware I/O planning for chip design, they can reduce costs through die-size reduction, the use of less expensive package technology, and reduced package complexity. Additionally, package-aware I/O planning enables hardware design teams to get early information about the type of packaging needed for a specific design, helping manage cost and schedule projections.

Ignoring the relationship between the chip, package, and PCB early in the design flow is no longer an option. What’s needed to build creative, innovative designs is an effective means of bridging the gap between the design of high-performance chips and packages, and a chip’s integration with the rest of the electronic system.

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EGINO SARTO, CTO, may be contacted at Rio Design Automation Inc., 2901 Tasman Drive, Suite 112, Santa Clara, CA 95054; 408/844-8038; E-mail: [email protected].


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