April 26, 2006 – Cadence Design Systems Inc., San Jose, CA, is releasing a revised system interconnect design platform to simplify and streamline designs for printed circuit boards, extending a “segmented” product strategy already used with its verification and digital-IC design product lines.
The Allegro now platform comes in three versions: Allegro L, for addressing mainstream design challenges; Allegro XL, targeting more complex and high-end design challenges through constraint-driven automation and distributed team-based design productivity; and Allegro GXL, geared toward leading-edge design challenges such as advanced package codesign and multi-GHz signal-integrity (SI) analysis.
A new addition to the Allegro XL series, Design Workbench XL, provides component information and library management for Allegro design libraries, automates library revision control, and offers a process for distributing known-good libraries to company design centers around the world. Cadence claims the Design Workbench helps shorten design cycles and reduces component research by up to 50%. Designs produced with Allegro Design Entry HDL can be published in PDF files using the platform’s Design Publisher feature, so that both internal and external design teams can review a design without requiring Cadence design entry tools.
A new board-level bus-analysis capability has been added to Allegro PCB SI, shortening time to verify source-synchronous signals used in interfaces such as DDR2 memories. Other enhancements associated with source-synchronous interfaces include support for on-die termination (ODT), association of clock, strobe signals to the bus, association of board-level custom stimulus, and reports for setup and hold times. Allegro PCB Editor also has been enhanced to shorten the time required to identify critical nets that will potentially have a return path problem.
“The ability to assign custom stimulus with jitter on nets at the board level and to assign different clock speeds to nets has made batch mode analysis of all types of interfaces significantly simpler,” said Kai Keskinen, engineering manager at Celestica, in a statement. “With set up at board level, the overall simulation of interfaces with source synchronous signals is significantly faster.”
Allegro L, XL, and GXL will be available in July 2006.