Design for Yield – A Hot Term for an Old Concept


Achieving design for yield (DFY) has more to do with effectively managing the IC design process than it does with introducing a new generation of software tools. True DFY balances economics and performance through a combination of designing for application compatibility, technical performance, low cost, and capitalization on the window of opportunity. The net objective is to reach the market quickly with a reliable product that meets or exceeds customers’ expectations, and results in a strong payback on R&D, ongoing profitability, and a competitive advantage. Failing to optimize the mix can cost a device manufacturer in R&D and months of time that cannot be recouped, not to mention the likelihood that the opportunity will be lost to a competitor.

Analysis and Planning is the Key

Assume we are an IC manufacturer developing a complex system-on-a-chip (SoC). We have analyzed the economic drivers behind the opportunity and have decided to move forward with development. At this point, consider the technical or performance drivers by evaluating the customers’ system. Assess compatibility with the customers’ environment, including power supplies, power dissipation, operating frequency, and I/O requirements. In the end, we verify that we can provide the right features, running at the right operating conditions, to satisfy the customers’ requirements for this next-generation system.

Once all aspects of the customers’ requirements are understood, chip planning begins by selecting the process to be used, evaluating its compatibility with chip requirements, studying die size vs. defect density to determine if the SoC can be built at a cost that enables a good profit margin. It is also critically important to consider the IC package performance because packages are expensive. We study performance requirements and develop an accurate cost model based on first-pass functionality to determine the affordable margin of error.

Once satisfied, we work closely with the various design organizations to verify that the SoC can get to production in the time frame required to meet the window of opportunity. Designers are always under pressure to get the job done yesterday, and to get it done right the first time. There is simply no time for numerous design iterations, yet we cannot afford to pay for more than one complete mask set at $1M each and lose an additional 4 to 6 months of R&D time. Although DFY tools are emerging and evolving quickly as necessary components of the overall design flow to assure engineers that their designs are optimized and manufacturable, much of the intelligence comes from the expertise of the design team itself, especially at the nanometric regime.

As complex ICs advance from 0.13-µm to 65-nm technology, operating frequencies increase, on-chip voltage supplies decrease, and power dissipation decreases. There is tighter timing between various I/Os, and any signal distortion can trigger intermittent errors and lead to chip failure. Although design tools that layout complex ICs exist, most do not deal with high-frequency or high-current switching challenges effectively, forcing designers to adopt tools and methodologies for simulating and analyzing the signal and power integrity of a design.

Optimizing the Mix

In today’s IC space, the challenges are enormous and the competition is fierce. The key to success is minimizing time-to-market. The penalty for missing the window is severe. Even perfectly implementing DFY, it is essential to be realistic. We want to be cost-effective and performance-efficient, but in reality, we must plan for and cost-in a certain amount of slippage and error, and meticulously manage the design process to come in early and under budget. We can tolerate some slippage and error, but beyond a certain point, the situation quickly becomes a crisis. When this occurs, IC companies cannot recoup the R&D spending or the time that has passed, and run the risk of losing ground to a competitor. An entire generation of product might be missed, resulting in heavy implications to the bottom line or the loss of an entire strategic market segment; and that is simply intolerable. Achieving DFY requires a balanced outlook on all variables.

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LEN PERHAM, chairman, may be contacted at Optimal Corp., 6980 Santa Teresa Blvd., Suite 100, San Jose, CA 95119; 408/363-6300; E-mail: [email protected].


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