April 18, 2006 – Cadence Design Systems Inc., San Jose, CA, and networking startup Teranetics Inc., Santa Clara, CA, have implemented Teranetics’ 10Gbit Ethernet (10GBase-T) chips using the X Architecture design layout.

“We are very excited with the remarkable reduction in power consumption demonstrated by the Cadence X Architecture design solution and plan to leverage it for our designs at advanced process nodes,” stated Sanjay Kasturia, CEO of Teranetics.

The X Architecture utilizes diagonal interconnects instead of the traditional right-angle layout resembling Manhattan street grids, which proponents say can shorten wiring by up to 20% across a die and reduce the number of vias by 30%.

Recent news reports quoted a Cadence exec saying that using X Architecture layouts with 0.13-micron process technologies to make 30 sq. m, 3-million-gate microprocessor cores, increased net die/wafer by 13% on 200mm wafers, and by 12% on 300mm wafers.

Last October, TSMC said it had qualified X Architecture design rules with Cadence on its Nexsys 90nm process, four months after producing a high-volume graphics processor with X Architecture using 0.11-micron process technologies. United Microelectronics Corp. (UMC) qualified 90nm process design rules for X Architecture-based chips in April 2005.