ITRS 2005: Focus on Assembly and Packaging

“Assembly and packaging are limiting factors in both cost and performance for electronic systems,” states the latest version of the International Technology Roadmap for Semiconductors (ITRS), published in December 2005. The Assembly and Packaging (A&P) chapter lists near-term “difficult challenges” in the areas of new materials, wafer-level packaging, chip/package/substrate co-design, embedded components, thinned-die packaging, organic substrates, high-current-density packages, flexible substrates, 3-D packaging, and fine-pitch packages. The greatest of these is R&D investment, which is inadequate to meet technical requirements, despite recent increases in packaging R&D from universities, research institutes, suppliers, and OEMs. The consumer-driven market squeezes margins of the A&P suppliers, limiting R&D spending.

(April 18, 2006) Irvine, CA &#8212 Brian Toleno, Ph.D., of the electronics group of Henkel will speak at the IMAPS Symposium, April 26, 2006, in Algonquin Heights, IL. Toleno, considered an electronics materials expert, will cover underfill technologies and their role in reliability enhancement for advanced CSP and BGA devices. The presentation will also offer an overview of a successful lead-free process implementation.


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