Samsung tips 3D memory package

April 13, 2006 – Samsung Electronics Co. Ltd. said it has developed a wafer-level processed stack package (WSP) of high-density memory chips that is 15% smaller and 30% thinner than an equivalent wire-bonded multichip package, using “through silicon via” interconnections.

The device incorporates eight 2Gbit NAND flash chips, each 50 microns high, vertically stacked to a height of 0.56mm.

Using WSP, micron-sized holes are drilled through the silicon vias instead of using conventional dry etching method, elmiinating photolithography processes required for mask-layer patterning and shortening dry-etching process needed to penetrate through a multilayer structure.

The WSP process also reduces the length of the interconnects, resulting in a 30% performance increase due to reduced electrical resistance, the company noted.

Samsung plans to apply the WSP packaging technique initially for its NAND-based memory cards in early 2007, and later to more high-performance system-in-package (SiP) and high-capacity DRAM stacks.


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