by Ed Korczynski, Senior Technical Editor, Solid State Technology
With costs soaring to support nanometer-era IC production, has the fabless industry finally come the point where widespread consolidation is imminent? Or, can fabless companies continue to operate much as they have for the last 15+ years? Daniel Gitlin, VP of semiconductor technology for Xilinx, presented ideas for a new business model for fabless companies in his presentation during the first day of The ConFab in Las Vegas, NV.
In the late 1980s, the rising costs of development and manufacturing led to forecasts that the industry would not have room for small companies to exist, and consolidation seemed inevitable. However, with the emergence of dedicated “pure-play” manufacturing foundries and fabless semiconductor companies, the only consolidation that occurred was in commodity chip markets such as DRAM.
Today, Gitlin offered, a primary consideration for a fabless company is the “virtual integration” that can be established with the rest of the industry. How much integration is needed? How much will such integration cost to establish as well as to maintain over time? At present, as the level of complexity that must be managed in nanometer-era production rises, so do the inevitable integration costs.
Fabless companies see themselves not as in the middle of a vertical supply chain, but in the middle of horizontal network including IP-providers, EDA/CAD suppliers, wafer foundries, test and packaging houses, and their own sales force, Gitlin noted. Relationships are dynamic and evolve over time. The fabless business model is inherently “open” in that core competencies are explicitly defined and everything else is open for discussion in terms of sourcing. Consequently, he said, the “confidence space” is much smaller than at an IDM, and dialog with partners can be more innovative.
Fabless companies, then, have the potential to adopt newer technologies from partners sooner than IDMs, Gitlin concluded. One area in which innovation may occur is optimizing the ROI associated with developing ICs for newer nanometer-era manufacturing nodes. To address DFM challenges, new communications channels must be established between foundries and fabless companies, he suggested -or else either the most advanced designs simply will not yield in silicon, or excessive “guard-banding” will eliminate the benefit of manufacturing at the newest node.
Gitlin proposed two fundamental strategies that fabless companies can employ to contain escalating development costs: create “standard” products with high volumes over time, and invest in DFM and yield engineering. The latter strategy is, of course, available to any fabless company regardless of current product mix, so it may be considered as relatively less disruptive to company and to its IP providers and sales force.
The full-flow and short-loop test chips that run through a foundry partner’s fab are the critical link in all of this, Gitlin said (SEE CHART, BELOW). Test chips provide the most rigorous DFM information to all interested parties, including the ability to diagnose physical failure mechanisms that correlate to electrical failure modes. Short-loop test chips for transistors and for interconnects can be iterated through the wafer foundry and the test house, to update yield models and determine if changes should be made to the processor to the design.
In the near future, successful fabless companies must continue to maintain all of their existing partner/supplier relationships, while intelligently embracing new DFM technologies and methodologies. The additional investment in DFM may pay for itself in improved yields, but it may just represent increased costs that must be averaged out across the bottom line. Just as the manufacturing processes needed to produce chips have increased in complexity, so too must the business models used by fabless companies. More complex business models involving flexible, horizontal, cross-functional organizations will allow the fabless industry to avoid the fate of consolidation. — E.K.