CHIPS: Defects dodged at the nanoscale level

compiled by Karen Moltenbrey

CHIPS: Defects dodged at the nanoscale level

Defects in fabrication and errors during operation will become a fact of life for electronic circuits at the nanoscale. To compensate, researchers are crafting schemes to correct fabrication defects and processing errors on the fly. Georgia Institute of Technology, with funding from Intel Corp., is pioneering probabilistic CMOS to trade off processing errors for cooler-running temperatures. And Hewlett-Packard Co. recently demonstrated a chip that uses massive redundancy and automatic recovery to compensate for fabrication errors in a 100G bit/cm2 nanowire storage array. HP’s current demonstration used nanoimprint lithography to fabricate 15-nanometer-wide wires with just 19 nm between their edges.

Model food-emergency response plan released

The Food and Drug Administration (FDA), in cooperation with the National Association of State Departments of Agriculture (NASDA), USDA’s Food Safety and Inspection Service (FSIS), and the Department of Homeland Security (DHS), has announced the availability of a model Food Emergency Response Plan Template. The goal of the response plan is to enhance the protection of the nation’s agricultural industry and food security through prevention, detection, response, and recovery.

The template provides states with a guide to develop either a stand-alone emergency response plan for responding to a food-related emergency or an addendum to an existing all-hazard state emergency response plan.

Because a food emergency could occur at any point from farm to fork, including pre-harvest production, processing, and distribution, states can use the template to develop useful plans to manage a food emergency. In addition, states can establish a uniform structure and content that will result in response plans that are similar in structure, scope, and response operations among all states.


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