Economics of sub-45nm chipmaking for equipment suppliers

By Bob Haavind, Editorial Director, Solid State Technology

Tough challenges facing process tool vendors as the industry moves toward sub-45nm chip features will require imaginative solutions. An analysis relating important application trends to process tool requirements was presented by Masayuki Tomoyasu, director of development and planning for Tokyo Electron, Ltd. (TEL), who then proposed a wide range of potential solutions for toolmakers.

The biggest problem facing toolmakers is that R&D requirements will rise rapidly as sub-45nm chipmaking calls for new materials and processes, and even new device structures. At the same time, chipmakers are requiring increased productivity and higher yields for diverse-purpose tools, according to Tomoyasu. How can these escalating requirements be met with affordable R&D investments?

That’s a possibly insurmountable challenge for any single company, he suggested, but he described a number of emerging and potential collaboration modes that might improve results within budget constraints.

Toolmakers are wary of overspending on R&D after the painful transition to 300mm wafers, Tomoyasu pointed out. In all previous wafer size shifts, R&D costs for toolmakers did not exceed US$200 million a year across the industry, but there was a huge surge in spending required for the 300mm transition. In 1997, R&D costs topped $1.5 billion, he said, but in spite of this huge spending no market developed for 300mm/0.25µm equipment. Costs then soared to more than $3 billion by 2001, according to VLSI Research, forcing R&D spending for major toolmakers to nearly 20% of revenues, and severely chopping profits. By 2004, Tomoyasu indicated, R&D had dropped back to a more traditional range at about 12% of revenues.

Now R&D pressures are rising again, not for a wafer size change but rather to meet new demands on chip designs. High growth markets for chips are in the consumer area, including mobile handsets, digital cameras, entertainment centers, personal digital assistants, and automotive electronics, for example. These are highly competitive, fast-paced markets with tight margins, putting price pressure on chipmakers in spite of added complexity. Many mobile applications will combine multiple functions. Home networks with interlinked computers, telecommunications, internet access, and TV-based devices will demand high performance along with new capabilities, such as remote operation.

This growth will escalate globally, Tomoyasu predicted, because of factors such as digital TV broadcasting, the 2008 Olympics in Beijing, and broadening of digital networks worldwide, especially in developing countries.

These trends are pushing process technology. Mobile devices will require low power along with increasing performance, forcing use of high-k gate dielectrics and high-k film formation for memory devices. High circuit densities will force shrinking design rules, so that immersion litho technology with extensive resolution enhancement will be needed. Home servers along with graphics and video requirements call for faster circuits, requiring ultralow-k film formation, low-k etching and deposition, whether by spin-on or CVD. Mobility engineering will also be essential. Achieving all of this at high productivity will mean increased process control, with in-line monitoring, and design for manufacturing (DFM) techniques.

Meeting all these application requirements will bring greater technology diversification, Tomoyasu said, but it will also create huge new business opportunities for those who can meet the challenges (see chart, below). The potential big payoffs will mean continuing efforts to accomplish all of these things effectively in spite of tight cost constraints.

What does all this mean to the process tool industry? Lithography is already moving to 193nm argon fluoride lasers with immersion to boost numerical aperture, while R&D continues on EUV (soft X-ray) technology for future nodes. Advanced gates/channels will need high-k dielectrics and metal gates, along with new structures for strain and channel engineering, according to Tomoyasu. Interconnects will call for ultralow-k inter-layer-dielectrics (ILDs) plus thinner barrier and seed layers for copper.

Tool productivity is being pushed along with higher yields, Tomoyasu noted. Throughput is being increased while defect counts are lowered. Tool matching is required, along with shorter ramp times, while tool costs are sometimes being lowered.

The industry is struggling to accomplish all of this with greater R&D cost efficiency — these costs must be pushed down perhaps 20%-30%/node if equipment vendors are to survive, Tomoyasu believes. At the same time, R&D cycle times are being compressed in spite of more diverse process demands and the need for highly integrated processes.

Collaboration in many forms will be essential to make this work, according to Tomoyasu, since individual companies will no longer be able to do all this on their own. Some improvements can be made inside each company. Capital spending can be minimized along with some utilization of lower cost labor. Concurrent engineering can be employed to develop tools with higher throughput and better overall equipment effectiveness (OEE), and also to devise new processes. First run rates can be improved as well, he added.

Strategic alliances externally will also be needed, however, such as with consortia, universities and national laboratories, and even with venture businesses. Tight focus, within companies and across the industry, will be needed to make all this work smoothly and effectively, Tomoyasu believes. Real challenges must be understood, including root causes that jeopardize productivity, for example.

Two-way communication between device makers and equipment and materials suppliers must be improved to accomplish this, in Tomoyasu’s view. There needs to be open discussion about productivity that includes chipmakers, equipment vendors, and materials suppliers as well. Equipment suppliers also need to share more fab productivity data with device makers in some appropriate way, he suggested.

Standards are important to narrow focus, and Tomoyasu cited some successful industry-wide efforts (GEM 300, FOUP, EFEM). But there are also cases where there are too many standards, he suggested, such as various interpretations of S-2, CE marking, and S mark. There are other areas where he believes standards could help, e.g., for substrates, factory and host interfaces, and perhaps even utility interfaces. Standards only have meaning, however, he pointed out, when they are used.

Consortia collaboration also must be carefully targeted. The latest process integration capability commencing with state-of-the-art lithography is essential, for example. Flexibility and bandwidth for research themes is preferable as technology advances, he suggested. Work must be carefully selected to avoid competitive versus pre-competitive issues. There also should be joint R&D platforms for member company participation.

Individual device manufacturers sometimes may have requirements that conflict with consortia, Tomoyasu suggested. This could lead to differences on short-term versus long-term time scales, for example. In such cases, it is important to be selective in organizing collaborative programs.

Universities and national labs can also be important in the mix, he believes. Putting consortia work right into some universities could be an efficient way to link work to industry requirements and to get feedback. But in these cases it is essential, he pointed out, to make effective use of the strengths of each university. Some might specialize in either disruptive technology or fundamental scientific research, for example. Mechanisms need to be clearly established to support more stable process/tool development and to achieve higher performance.

In general, however, he suggested, university-based research will not help much with R&D cost reduction for short-term results.

One alternative might be greater collaboration among process tool vendors. While some work like this already exists, Tomoyasu sees potential in areas such as scanners/tracks, CVD/surface preparation, and etch/lithography. Process tool suppliers can also work with automation vendors and software developers.

In all of these efforts, Tomoyasu urged, it is vital to concentrate on technology that will be most effective and has the greatest probability of adoption by the market. Device makers need to share correct, factual information about future needs and targets with existing industry groups, such as SEMI, ISMI, JEITA, KSIA, TSIA, etc., to avoid wasteful R&D efforts. — By Bob Haavind


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