IMEC extends Ge, III-V work to sub-22nm CMOS

May 18, 2006 – European microelectronics consortium IMEC and Riber, a French supplier of molecular beam epitaxy (MBE) technology for compound semiconductors, are collaborating to introduce germanium (Ge) and III-V materials for CMOS scaling beyond the 22nm manufacturing node and beyond.

Ge has been touted as a potential replacement for planar silicon due to higher mobility, resulting in lower intrinsic gate delay. Last year IMEC demonstrated feasibility of sub-micron pMOS devices on GeOI substrates. Now, IMEC will look at III-V nMOS devices on the same Ge substrates, with the process based on silicon wafers to enable manufacturing in a standard silicon process line using CMOS-compatible equipment. Among the programs goals is to improve the gate stack for MOS
devices on Ge as well as on III-V compounds.

Under IMEC’s Industrial Affiliation Program, the two groups will utilize Riber’s ultrahigh-vacuum MBE cluster system for 200mm wafers, which incorporates a III-V semiconductor growth chamber and a metal/oxide deposition chamber, to deposit compound semiconductor layers on GeOI or other Ge substrates, and deposit high-k dielectrics and metal gates on Ge and on III-V materials.

The Ge and III-V devices program is part of IMEC’s sub-45nm CMOS research platform, with participation from Infineon, Intel, Matsushita/Panasonic, Philips, Samsung, ST Microelectronics, Texas Instruments, and TSMC.

IMEC and Riber say they also plan to extend the technology into photonics applications.


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