PoP as a Preferred Packaging Solution

Package-on-package (PoP) has emerged asthe preferred 3-D packaging solution for integration of logic and high-performance memory devices in mobile multimedia products. PoP development was driven by the needs of leading mobile phone OEMs to reduce total cost-of-ownership and remove supply chain limitations for integrating baseband, multimedia processing, and combination memory devices.

To integrate complex devices from different suppliers into the same 3-D socket footprint, the OEM had to take control of the stacking responsibility in their system design and final assembly flows. Prior to PoP, stacked die in chip scale package (CSP) platforms provided the 3-D system-in-package (SiP) component. A SiP may offer small package size and low combined packaging cost, but it requires known good die (KGD) in wafer supply to be cost-effective, which is a limitation for processor or memory devices.

Device and supplier selection must be done early in the design cycle of SiP integration to allow for the long component development schedules. High interconnect wiring density, compound yield loss, multi-insertion testing and gross margin stacking, non-recurring engineering (NRE) or time-to-market penalties, and component supply flexibility are major limitations when logic suppliers must purchase memory wafers for integration in a SiP.

PoP solves these issues by allowing OEMs to source logic and memory packages separately and stack the mating components in their final surface mount assembly flow. OEMs now have flexibility to source logic or memory components from multiple sources and have a highly flexible and scaleable 3-D platform to expand on for further integration and cost reduction. Standardized memory interfaces, along with independent memory supply, gives OEMs the capability to change memory configurations late into the design cycle, or to easily change memory content for different models. PoP reduces total system costs by eliminating SiP limitations, and using standard business model component assembly and test flows.

Today, PoP configurations in digital still cameras (DSCs) tend to be customized for each product, while standard configurations for multimedia handsets are being defined to realize the full supply chain flexibility benefits. The JEDEC JC11 committee has published a PoP design guide and defined standard package outline for the bottom logic PSvfBGA packages in registration MO-266. A similar registration is currently in ballot for the mating top memory package. JEDEC JC-63 has defined several standard pinouts for the memory interface, enabling a range of memory architectures and true dual-source flexibility for memory supply. The basic straddle-mount PoP configuration is an open source technology allowing broad industry adoption.

OEMs and EMS providers are reporting PoP surface mount yields in line with 0.5-mm-pitch FBGA assembly yields. The preferred process for PoP stacking is to print solder paste and place the bottom package on the board as normal, then dip the top package in tacky flux or paste and place onto the top lands of the bottom package. A single reflow is used to solder both packages at the same time as all other components on the board. Since the top and bottom packages are free to move independently during reflow, it is critical to control flatness of both packages to ensure good stacking yield. In particular, the package flatness at the reflow temperature must be engineered such that the magnitude and direction of warpage is similar for both packages during solder joint formation.

The first PoP used in cell-phone production in 2004 was a 14 × 14-mm PoP base package with a single wire-bonded baseband die. A stacked-die CSP containing 3 memory dice was mounted to the base package using a 2-row, 0.65-mm-pitch BGA interface. A number of enhancements to this basic PoP structure are being introduced in 2006. Stacked die in the base package will be implemented in production. Integration of higher-pin-count die with multiple wire-loop heights is becoming standard as more dual-core processors are being integrated. Both of these will increase the thickness of the mold cap on the base package. Simultaneously, the pitch of the memory interface is being reduced from 0.65- to 0.5-mm pitch to reduce package body size and/or increase memory-interface pin count.

Techniques, such as bumping the base package BGA pads, are being developed to maintain adequate gap height between the base package and memory CSP. Many baseband IC suppliers have a roadmap to transition from wire-bond to flip chip interconnect. Flip chip PoP base packages have recently been introduced to support this transition.

Click here to enlarge image

CHRISTOPHER SCANLAN, VP of packaging development, may be contacted at Amkor Technology, 1900 South Price Rd., Chandler, AZ 85248; 480/821-6730; E-mail: [email protected].


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.